JosephTheOctonaut commented on code in PR #12785: URL: https://github.com/apache/tvm/pull/12785#discussion_r973390163
########## src/tir/transforms/lower_async_dma.cc: ########## @@ -0,0 +1,172 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/*! + * \file lower_async_dma.cc + */ + +#include <tvm/arith/analyzer.h> +#include <tvm/tir/stmt_functor.h> +#include <tvm/tir/transform.h> + +#include "ir_utils.h" + +namespace tvm { +namespace tir { + +class AsyncDMALowerer : public StmtExprMutator { + public: + AsyncDMALowerer() {} + + Stmt VisitStmt_(const AttrStmtNode* op) final { + // Convert this, for example: + // attr [0] "async_wait_queue_scope" = 0; + // attr [0] "async_wait_inflight_count" = 0; + // + // To this: + // @tir.dma_wait( + // 0, /* queue id */ + // 0, /* in flight count */ + // dtype=int32 + // ) + if (op->attr_key == tir::attr::async_wait_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // abort if we have not seen this queue ID in `copy` transform + if (queue_ids.find(queue_id) == queue_ids.end()) { Review Comment: This check implies that `dma_wait` must always follow the corresponding `dma_copy` in program order. Since the `dma_copy` is asynchronous, it's not strictly necessary for correctness that it show up first. It seems fine for now to require that the stages show up in a specific order, but an error or debug message might be helpful here to clarify why the transform isn't doing anything. ########## src/tir/transforms/lower_async_dma.cc: ########## @@ -0,0 +1,172 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/*! + * \file lower_async_dma.cc + */ + +#include <tvm/arith/analyzer.h> +#include <tvm/tir/stmt_functor.h> +#include <tvm/tir/transform.h> + +#include "ir_utils.h" + +namespace tvm { +namespace tir { + +class AsyncDMALowerer : public StmtExprMutator { + public: + AsyncDMALowerer() {} + + Stmt VisitStmt_(const AttrStmtNode* op) final { + // Convert this, for example: + // attr [0] "async_wait_queue_scope" = 0; + // attr [0] "async_wait_inflight_count" = 0; + // + // To this: + // @tir.dma_wait( + // 0, /* queue id */ + // 0, /* in flight count */ + // dtype=int32 + // ) + if (op->attr_key == tir::attr::async_wait_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // abort if we have not seen this queue ID in `copy` transform + if (queue_ids.find(queue_id) == queue_ids.end()) { + return StmtExprMutator::VisitStmt_(op); + } + + auto async_wait = op->body.as<AttrStmtNode>(); + ICHECK(async_wait && async_wait->attr_key == tir::attr::async_wait_inflight_count); + + auto call_dma_wait = + Evaluate(Call(DataType::Int(32), builtin::dma_wait(), {queue_id, async_wait->value})); + + // concatenate the call with the body and return + return SeqStmt({call_dma_wait, async_wait->body}); + + // Convert this, for example: + // attr [0] "async_commit_queue_scope" = 0; + // attr [0] "async_scope" = 1; + // for (ax0: int32, 0, 128) { + // A_global[ax0] = A[ax0] + // } + // + // To this: + // @tir.dma_copy( + // 0, /* queue id */ + // @tir.address_of(A_global[0], dtype=handle), + // @tir.address_of(A[0], dtype=handle), + // 128, /* size */ + // dtype=int32 + // ) + } else if (op->attr_key == tir::attr::async_commit_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // save queue ID for inspection in `wait` transform + queue_ids.insert(queue_id); + + // walk the graph to verify this is a mem copy ... + // 1) async_commit_queue_scope contains async_scope + auto async_scope = op->body.as<AttrStmtNode>(); + ICHECK(async_scope && async_scope->attr_key == tir::attr::async_scope); + + // 2) async_scope contains single for loop + auto for_loop = async_scope->body.as<ForNode>(); + if (!for_loop) { + return StmtExprMutator::VisitStmt_(op); + } + + // 3) for loop contains buffer store with single index + auto bufferstorenode = for_loop->body.as<BufferStoreNode>(); + if (!bufferstorenode || bufferstorenode->indices.size() != 1) { + return StmtExprMutator::VisitStmt_(op); + } + + // 4) buffer store value is a buffer load with single index + auto bufferloadnode = bufferstorenode->value.as<BufferLoadNode>(); + if (!bufferloadnode || bufferloadnode->indices.size() != 1) { Review Comment: This check, along with L99 and L105, would have the transform fail silently. A debug message might be helpful to explain why the transform couldn't run. ########## src/tir/transforms/lower_async_dma.cc: ########## @@ -0,0 +1,172 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/*! + * \file lower_async_dma.cc + */ + +#include <tvm/arith/analyzer.h> +#include <tvm/tir/stmt_functor.h> +#include <tvm/tir/transform.h> + +#include "ir_utils.h" + +namespace tvm { +namespace tir { + +class AsyncDMALowerer : public StmtExprMutator { + public: + AsyncDMALowerer() {} + + Stmt VisitStmt_(const AttrStmtNode* op) final { + // Convert this, for example: + // attr [0] "async_wait_queue_scope" = 0; + // attr [0] "async_wait_inflight_count" = 0; + // + // To this: + // @tir.dma_wait( + // 0, /* queue id */ + // 0, /* in flight count */ + // dtype=int32 + // ) + if (op->attr_key == tir::attr::async_wait_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // abort if we have not seen this queue ID in `copy` transform + if (queue_ids.find(queue_id) == queue_ids.end()) { + return StmtExprMutator::VisitStmt_(op); + } + + auto async_wait = op->body.as<AttrStmtNode>(); + ICHECK(async_wait && async_wait->attr_key == tir::attr::async_wait_inflight_count); + + auto call_dma_wait = + Evaluate(Call(DataType::Int(32), builtin::dma_wait(), {queue_id, async_wait->value})); + + // concatenate the call with the body and return + return SeqStmt({call_dma_wait, async_wait->body}); + + // Convert this, for example: + // attr [0] "async_commit_queue_scope" = 0; + // attr [0] "async_scope" = 1; + // for (ax0: int32, 0, 128) { + // A_global[ax0] = A[ax0] + // } + // + // To this: + // @tir.dma_copy( + // 0, /* queue id */ + // @tir.address_of(A_global[0], dtype=handle), + // @tir.address_of(A[0], dtype=handle), + // 128, /* size */ + // dtype=int32 + // ) + } else if (op->attr_key == tir::attr::async_commit_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // save queue ID for inspection in `wait` transform + queue_ids.insert(queue_id); + + // walk the graph to verify this is a mem copy ... + // 1) async_commit_queue_scope contains async_scope + auto async_scope = op->body.as<AttrStmtNode>(); + ICHECK(async_scope && async_scope->attr_key == tir::attr::async_scope); + + // 2) async_scope contains single for loop + auto for_loop = async_scope->body.as<ForNode>(); + if (!for_loop) { + return StmtExprMutator::VisitStmt_(op); + } + + // 3) for loop contains buffer store with single index + auto bufferstorenode = for_loop->body.as<BufferStoreNode>(); + if (!bufferstorenode || bufferstorenode->indices.size() != 1) { + return StmtExprMutator::VisitStmt_(op); + } + + // 4) buffer store value is a buffer load with single index + auto bufferloadnode = bufferstorenode->value.as<BufferLoadNode>(); + if (!bufferloadnode || bufferloadnode->indices.size() != 1) { + return StmtExprMutator::VisitStmt_(op); + } + + // get store buffer and assert that it is contiguous + auto bufferstore = bufferstorenode->buffer.as<BufferNode>(); + ICHECK(bufferstore && bufferstore->strides.empty()); + + // get load buffer and assert that it is contiguous + auto bufferload = bufferloadnode->buffer.as<BufferNode>(); + ICHECK(bufferload && bufferload->strides.empty()); + + // we will be replacing the entire for loop including its index + // with a DMA copy instrinsic that spans the entire index space of the for loop + // so we will need to repace the for loop index with value zero in the buffer indices Review Comment: If I understand, the purpose of this is to eliminate the index from the expression so the DMA copy receives the buffer range base address, correct? ########## src/tir/transforms/lower_async_dma.cc: ########## @@ -0,0 +1,172 @@ +/* + * Licensed to the Apache Software Foundation (ASF) under one + * or more contributor license agreements. See the NOTICE file + * distributed with this work for additional information + * regarding copyright ownership. The ASF licenses this file + * to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance + * with the License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, + * software distributed under the License is distributed on an + * "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY + * KIND, either express or implied. See the License for the + * specific language governing permissions and limitations + * under the License. + */ + +/*! + * \file lower_async_dma.cc + */ + +#include <tvm/arith/analyzer.h> +#include <tvm/tir/stmt_functor.h> +#include <tvm/tir/transform.h> + +#include "ir_utils.h" + +namespace tvm { +namespace tir { + +class AsyncDMALowerer : public StmtExprMutator { + public: + AsyncDMALowerer() {} + + Stmt VisitStmt_(const AttrStmtNode* op) final { + // Convert this, for example: + // attr [0] "async_wait_queue_scope" = 0; + // attr [0] "async_wait_inflight_count" = 0; + // + // To this: + // @tir.dma_wait( + // 0, /* queue id */ + // 0, /* in flight count */ + // dtype=int32 + // ) + if (op->attr_key == tir::attr::async_wait_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // abort if we have not seen this queue ID in `copy` transform + if (queue_ids.find(queue_id) == queue_ids.end()) { + return StmtExprMutator::VisitStmt_(op); + } + + auto async_wait = op->body.as<AttrStmtNode>(); + ICHECK(async_wait && async_wait->attr_key == tir::attr::async_wait_inflight_count); + + auto call_dma_wait = + Evaluate(Call(DataType::Int(32), builtin::dma_wait(), {queue_id, async_wait->value})); + + // concatenate the call with the body and return + return SeqStmt({call_dma_wait, async_wait->body}); + + // Convert this, for example: + // attr [0] "async_commit_queue_scope" = 0; + // attr [0] "async_scope" = 1; + // for (ax0: int32, 0, 128) { + // A_global[ax0] = A[ax0] + // } + // + // To this: + // @tir.dma_copy( + // 0, /* queue id */ + // @tir.address_of(A_global[0], dtype=handle), + // @tir.address_of(A[0], dtype=handle), + // 128, /* size */ + // dtype=int32 + // ) + } else if (op->attr_key == tir::attr::async_commit_queue_scope) { + // get queue ID + auto queue_id_node = op->value.as<IntImmNode>(); + ICHECK(queue_id_node); + int queue_id = queue_id_node->value; + + // save queue ID for inspection in `wait` transform + queue_ids.insert(queue_id); + + // walk the graph to verify this is a mem copy ... + // 1) async_commit_queue_scope contains async_scope + auto async_scope = op->body.as<AttrStmtNode>(); + ICHECK(async_scope && async_scope->attr_key == tir::attr::async_scope); + + // 2) async_scope contains single for loop + auto for_loop = async_scope->body.as<ForNode>(); + if (!for_loop) { + return StmtExprMutator::VisitStmt_(op); + } + + // 3) for loop contains buffer store with single index + auto bufferstorenode = for_loop->body.as<BufferStoreNode>(); + if (!bufferstorenode || bufferstorenode->indices.size() != 1) { + return StmtExprMutator::VisitStmt_(op); + } + + // 4) buffer store value is a buffer load with single index + auto bufferloadnode = bufferstorenode->value.as<BufferLoadNode>(); + if (!bufferloadnode || bufferloadnode->indices.size() != 1) { + return StmtExprMutator::VisitStmt_(op); + } + + // get store buffer and assert that it is contiguous + auto bufferstore = bufferstorenode->buffer.as<BufferNode>(); + ICHECK(bufferstore && bufferstore->strides.empty()); + + // get load buffer and assert that it is contiguous + auto bufferload = bufferloadnode->buffer.as<BufferNode>(); + ICHECK(bufferload && bufferload->strides.empty()); Review Comment: Previous checks, if failed, cause the transform to fail gracefully. Why are these fatal failures? ########## include/tvm/tir/builtin.h: ########## @@ -720,6 +720,16 @@ TVM_DLL const Op& texture2d_load(); */ TVM_DLL const Op& mem_copy(); +/*! + * \brief Initiate a non-blocking DMA copy from source to destination + */ +TVM_DLL const Op& dma_copy(); + +/*! + * \brief Wait until the number of DMAs in flight is less than or equal to some maximum + */ +TVM_DLL const Op& dma_wait(); Review Comment: The tension in specific-vs-general intrinsics is trying to guess how "general" this style is. We have a good degree of certainty that the CUDA style is unique to PTX, but I would guess that most platforms with DMA engines could support an async copy() and wait() of this style? The risk in making it general is that we end up with DMA-enabled targets that need a different version. The risk in making it specific is that we end up with multiple target-specific intrinsics that are essentially identical. ########## include/tvm/tir/builtin.h: ########## @@ -720,6 +720,16 @@ TVM_DLL const Op& texture2d_load(); */ TVM_DLL const Op& mem_copy(); +/*! + * \brief Initiate a non-blocking DMA copy from source to destination + */ +TVM_DLL const Op& dma_copy(); + +/*! + * \brief Wait until the number of DMAs in flight is less than or equal to some maximum + */ +TVM_DLL const Op& dma_wait(); Review Comment: Regardless of the choice there, the pass should probably be Hexagon-specific. I think you had another comment @adstraw about breaking the existing async pipeline lowering --- I agree with that; this transform should be Hexagon-only and probably opt-in, since it's mutually exclusive (at the moment) with other async lowerings and destroys the async annotations. -- This is an automated message from the Apache Git Service. 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