tkonolige commented on code in PR #12856:
URL: https://github.com/apache/tvm/pull/12856#discussion_r981671533
##########
python/tvm/topi/arm_cpu/conv2d_alter_op.py:
##########
@@ -121,7 +124,33 @@ def _alter_conv2d_layout(attrs, inputs, tinfos, out_type):
idxd = tvm.tir.indexdiv
- # We don't perform layout alteration for NHWC layout with real data types
+ if topi_tmpl == "depthwise_conv2d_nhwc_dsp.arm_cpu":
+ assert data_layout == "NHWC" and kernel_layout == "HWOI"
+ channels = get_const_tuple(data.shape)[3]
+ KH, KW, _, _ = get_const_tuple(kernel.shape)
+ simd_width = get_dtype_simd_width(data.dtype)
+
+ HWOI_kernel_np = inputs[1].data.numpy()
Review Comment:
You'll need to check that the kernel is a constant and fallback to a
different implementation if it is not.
##########
python/tvm/topi/arm_cpu/mprofile/dsp/micro_kernel/common.py:
##########
@@ -29,3 +29,18 @@
#include <tvm/runtime/crt/error_codes.h>
"""
+
+MICRO_WORD_LENGTH = 32
+
+
+def get_dtype_simd_width(dtype: str) -> int:
Review Comment:
I'd also remove the "get". It doesn't add anything to the function name.
##########
python/tvm/topi/arm_cpu/mprofile/dsp/micro_kernel/multi_channel_convolve.py:
##########
@@ -0,0 +1,208 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+"""This is a special intrinsic used for depthwise convolution using Cortex-M
DSP instructions
+(v7e-m). It takes as inputs an int8 HWC data tensor and an int8 CHWc kernel.
This intrinsic "lays"
+the kernel on top of the data tensors starting from a given pointer, performs
signed sixteen-bit
+multiplies on each pair of values, and sums all the products in an int32
accumlator. This process is
+repeated four times giving four int32 outputs - one per channel."""
+
+import textwrap
+
+from tvm import te, tir
+from .common import get_dtype_simd_width
+
+
+def _get_func_name(in_dtype, tensor_w, channels, kernel_h, kernel_w, suffix):
+ """Gets the C function name of the tensorized function."""
+ return
f"kernel_convolve_{in_dtype}_w{tensor_w}_c{channels}_kh{kernel_h}_kw{kernel_w}_{suffix}"
+
+
+def intrin_multi_channel_convolve(
+ in_dtype, _tensor_h, tensor_w, channels, kernel_h, kernel_w, suffix
+):
+ """Defines a v7e-m DSP-accelerated multi-channel convolution. Works on two
+ channels if in_dtype==int16, and four channels if in_dtype==int8."""
+ simd_width = get_dtype_simd_width(in_dtype)
+ data_slice = te.placeholder((kernel_h, kernel_w, simd_width), name="a",
dtype=in_dtype)
Review Comment:
```suggestion
data_slice = te.placeholder((kernel_h, kernel_w, simd_width),
name="data_slice", dtype=in_dtype)
```
##########
python/tvm/topi/arm_cpu/mprofile/dsp/micro_kernel/multi_channel_convolve.py:
##########
@@ -0,0 +1,208 @@
+# Licensed to the Apache Software Foundation (ASF) under one
+# or more contributor license agreements. See the NOTICE file
+# distributed with this work for additional information
+# regarding copyright ownership. The ASF licenses this file
+# to you under the Apache License, Version 2.0 (the
+# "License"); you may not use this file except in compliance
+# with the License. You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing,
+# software distributed under the License is distributed on an
+# "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY
+# KIND, either express or implied. See the License for the
+# specific language governing permissions and limitations
+# under the License.
+"""This is a special intrinsic used for depthwise convolution using Cortex-M
DSP instructions
+(v7e-m). It takes as inputs an int8 HWC data tensor and an int8 CHWc kernel.
This intrinsic "lays"
+the kernel on top of the data tensors starting from a given pointer, performs
signed sixteen-bit
+multiplies on each pair of values, and sums all the products in an int32
accumlator. This process is
+repeated four times giving four int32 outputs - one per channel."""
+
+import textwrap
+
+from tvm import te, tir
+from .common import get_dtype_simd_width
+
+
+def _get_func_name(in_dtype, tensor_w, channels, kernel_h, kernel_w, suffix):
+ """Gets the C function name of the tensorized function."""
+ return
f"kernel_convolve_{in_dtype}_w{tensor_w}_c{channels}_kh{kernel_h}_kw{kernel_w}_{suffix}"
+
+
+def intrin_multi_channel_convolve(
+ in_dtype, _tensor_h, tensor_w, channels, kernel_h, kernel_w, suffix
+):
+ """Defines a v7e-m DSP-accelerated multi-channel convolution. Works on two
+ channels if in_dtype==int16, and four channels if in_dtype==int8."""
+ simd_width = get_dtype_simd_width(in_dtype)
+ data_slice = te.placeholder((kernel_h, kernel_w, simd_width), name="a",
dtype=in_dtype)
+ kernel_slice = te.placeholder((kernel_h, kernel_w, simd_width), name="b",
dtype=in_dtype)
Review Comment:
```suggestion
kernel_slice = te.placeholder((kernel_h, kernel_w, simd_width),
name="kernel_slice", dtype=in_dtype)
```
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