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from de6d806775 [CMSIS-NN] Support for int16 conv2d (#12950)
add 1ea1a0bc88 [Hexagon] 3-stage pipeline; multi queue async DMA for cache
read / write (#12954)
No new revisions were added by this update.
Summary of changes:
src/runtime/hexagon/hexagon_device_api.cc | 6 +-
src/runtime/hexagon/hexagon_user_dma.cc | 24 ++---
src/runtime/hexagon/hexagon_user_dma.h | 15 +--
src/runtime/hexagon/ring_buffer.h | 41 +++++++-
.../cpp-runtime/hexagon/hexagon_user_dma_tests.cc | 104 +++++++++++++++------
tests/cpp-runtime/hexagon/ring_buffer_tests.cc | 30 +++++-
.../test_hexagon/test_software_pipeline_async.py | 43 +++++++--
7 files changed, 196 insertions(+), 67 deletions(-)
