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from 7804a9886c [Hexagon] disable cache_write schedule type from sw
pipeline test (#13004)
add fc333f90e8 [TIR][Arith] Prove conditionals by transitively applying
knowns (#12863)
add d9e01475af [UnitTest][TIR] Support IRModule comparisons in
CompareBeforeAfter (#12920)
No new revisions were added by this update.
Summary of changes:
include/tvm/arith/analyzer.h | 114 ++-
python/tvm/testing/utils.py | 105 ++-
src/arith/analyzer.cc | 3 +
src/arith/canonical_simplify.cc | 10 +-
src/arith/rewrite_simplify.cc | 79 +-
src/arith/rewrite_simplify.h | 28 +-
src/arith/transitive_comparison_analyzer.cc | 791 +++++++++++++++++++++
src/tir/transforms/simplify.cc | 34 +-
.../python/unittest/test_tir_transform_simplify.py | 141 +++-
.../unittest/test_tvm_testing_before_after.py | 49 +-
10 files changed, 1289 insertions(+), 65 deletions(-)
create mode 100644 src/arith/transitive_comparison_analyzer.cc
