masahi commented on code in PR #13206:
URL: https://github.com/apache/tvm/pull/13206#discussion_r1007772390
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src/tir/schedule/primitive/cache_read_write.cc:
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@@ -297,7 +297,12 @@ bool CalculateAffineFlag(const ScheduleState& self, const
StmtSRef& block_sref)
* \param stage The stage to be inserted
* \return A SeqStmt, the result after insertion
*/
-SeqStmt InsertCacheStage(const Stmt& stmt, int pos, const Stmt& stage) {
+Stmt InsertCacheStage(const Stmt& stmt, int pos, const Stmt& stage) {
Review Comment:
Added a test case for this fix. For some reason I cannot reproduce this bug
without anchor tuning. So I'm including it here.
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