This is an automated email from the ASF dual-hosted git repository.
github-bot pushed a change to branch nightly-docker-update
in repository https://gitbox.apache.org/repos/asf/tvm.git
omit 0dbdb93e7f [ci][docker] Nightly Docker image update
add 93fdf83e8f [MetaSchedule] Improve inlining and `VerifyGPUCode` for
quantized model workload (#13334)
add f950b118aa [MetaSchedule][Minor] Allow Zero Run Time In Benchmarking
Result (#13354)
add 6d68aff030 [Bugfix][TIR] Patch for PR#13269 to support Python 3.10
(#13350)
add a15663654b [MetaSchedule] Unannotate `schedule_rule` if corresponding
schedule func is not found (#13346)
add f3eb239989 [MetaSchedule] Skip empty fx graph in TorchBench tuning
script (#13356)
add 5364e5a39a [MetaSchedule] Fuse loops around shared to global store
block in `MultiLevelTilingTensorCore` (#13357)
add 45327127d5 [TIR][Schedule] Make consistent implementation for
GetProducers() & GetConsumers() (#13344)
add f9ed60aaef [Relay] Refactor constant folding over expr into a utility
function (#13343)
add ce0e9abea0 [TIR] Make syntax of AST nodes different than ops (#13358)
add 5ffcfd9327 [FQ2I] Add cast back to input data type after AvgPool2d
(#13332)
add 8897983484 [IRBuilder][Minor] Add intrinsics like `T.int32x4` (#13361)
add 5dd0b68984 [ci][docker] Nightly Docker image update
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Summary of changes:
Jenkinsfile | 20 +-
ci/jenkins/Jenkinsfile.j2 | 20 +-
include/tvm/meta_schedule/schedule_rule.h | 10 +
include/tvm/script/ir_builder/tir/frame.h | 16 +-
include/tvm/script/ir_builder/tir/ir.h | 46 +-
python/tvm/meta_schedule/schedule_rule/__init__.py | 2 +-
.../tvm/meta_schedule/schedule_rule/auto_inline.py | 17 +
python/tvm/meta_schedule/testing/torchbench/run.py | 22 +-
.../transform/fake_quantization_to_integer.py | 7 +-
python/tvm/script/ir_builder/tir/frame.py | 4 +-
python/tvm/script/ir_builder/tir/ir.py | 473 +++++++++------------
python/tvm/script/tir/intrin.py | 80 +++-
python/tvm/tir/op.py | 57 ++-
python/tvm/tir/schedule/_type_checker.py | 13 +-
.../measure_callback/update_cost_model.cc | 3 +-
.../postproc/rewrite_cooperative_fetch.cc | 30 ++
src/meta_schedule/postproc/verify_gpu_code.cc | 2 +
.../schedule_rule/apply_custom_rule.cc | 1 +
src/meta_schedule/schedule_rule/auto_inline.cc | 37 ++
.../schedule_rule/multi_level_tiling.cc | 4 +-
.../multi_level_tiling_tensor_core.cc | 5 +
src/meta_schedule/schedule_rule/schedule_rule.cc | 3 +
src/meta_schedule/utils.h | 13 +
src/printer/tvmscript_printer.cc | 97 +++--
src/relay/backend/contrib/constant_transforms.cc | 10 +-
src/relay/backend/contrib/constant_transforms.h | 9 -
.../backend/contrib/ethosn/convert_equivalent.cc | 4 +-
src/relay/quantize/realize.cc | 18 +-
src/relay/quantize/realize.h | 2 -
src/relay/transforms/fold_constant.cc | 20 +-
.../fold_constant.h} | 30 +-
src/relay/transforms/simplify_expr.cc | 11 +-
src/script/ir_builder/tir/frame.cc | 14 +-
src/script/ir_builder/tir/ir.cc | 56 ++-
src/tir/analysis/verify_gpu_code.cc | 13 +
src/tir/schedule/analysis/analysis.cc | 34 +-
src/tir/schedule/primitive/get_block_loop.cc | 27 +-
.../metaschedule_e2e/test_resnet50_int8.py | 5 +-
.../test_hexagon/test_async_dma_pipeline.py | 17 +-
.../test_hexagon/test_parallel_hvx_load_vtcm.py | 49 +--
tests/python/integration/test_auto_tensorize.py | 1 +
.../test_pass_fake_quantization_to_integer.py | 21 +
.../unittest/test_aot_legalize_packed_call.py | 12 +-
.../test_meta_schedule_measure_callback.py | 28 +-
...test_meta_schedule_schedule_rule_auto_inline.py | 115 +++++
.../test_meta_schedule_schedule_rule_mlt_tc.py | 39 +-
.../unittest/test_meta_schedule_space_cuda.py | 2 +-
.../test_tir_transform_inject_software_pipeline.py | 16 +-
.../test_tir_transform_inject_virtual_thread.py | 17 +-
.../unittest/test_tir_transform_thread_sync.py | 2 +-
.../python/unittest/test_tvmscript_error_report.py | 2 +-
.../unittest/test_tvmscript_ir_builder_tir.py | 21 +-
tests/python/unittest/test_tvmscript_roundtrip.py | 8 +-
53 files changed, 969 insertions(+), 616 deletions(-)
copy src/relay/{backend/contrib/constant_transforms.h =>
transforms/fold_constant.h} (60%)
