masahi commented on PR #13446: URL: https://github.com/apache/tvm/pull/13446#issuecomment-1331988141
I made a new branch based on this PR, to apply `MultiLevelTilingHexagon` in practice: https://github.com/apache/tvm/compare/main...masahi:hex-ms-async?expand=1 Currently, tuning can run but the output is incorrect if async DMA is enabled. If we enable only VTCM cache read and synchronous software pipeline, the output is correct. See the test case in `test_hexagon/test_conv2d_async.py`. Here is an example of a generated IR after `LowerAsyncDMA`: https://gist.github.com/masahi/f15806cb19f5c00da10a12341aef137e The main changes from this PR are: * Start from `MultiLevelTilingWithIntrin`, rather than `MultiLevelTilingTensorCore`, to avoid unnecessary complications like `reindex` and `transform_layout`. * Using `AddReadReuse` with level `1` leads to `cache_read` block being placed under a spatial loop. The pipeline annotation is also attached to the wrong loop, which makes `DecomposeReduction` fail to place the initialization block outside of the pipeline loop. This results in an error `pipeline_stages.size() != original_order.size() (4 vs 3)` (the init block is counted as one of the blocks in the pipeline loop). Using `levels = [2]` fixes these issues. * Moreover, rather than pipelining only over a single reduction loop, fuse all reduction loops above a cache-read block. For example, in ``` for i0_0, i1_0, i2_0, i3_0, i4_0_0, i5_0, i6_0, i7_0, i8_0, i9_0_0 in T.grid(T.int64(1), T.int64(2), T.int64(6), T.int64(3), T.int64(1), T.int64(1), T.int64(3), T.int64(1), T.int64(4), T.int64(1)): for ax0_ax1_ax2_ax3_ax4_fused in T.serial(T.int64(3168)): with T.block("p0_global.vtcm"): ... for ax0_ax1_ax2_ax3_ax4_ax5_ax6_fused in T.serial(T.int64(1536)): with T.block("fused_constant_global.vtcm"): ... ``` `i5_0, i6_0, i7_0, i8_0, i9_0_0` are all reduction loops, which can be fused to make a bigger pipelined loop. After fusing and applying the annotations, it looks like: ``` for i0_0, i1_0, i2_0, i3_0, i4_0_0 in T.grid(T.int64(1), T.int64(1), T.int64(1), T.int64(1), T.int64(1)): for i5_0_i6_0_i7_0_i8_0_i9_0_0_fused in T.serial(T.int64(12), annotations={"software_pipeline_async_stages":[0], "software_pipeline_order":[0, 1, 2], "software_pipeline_stage":[0, 0, 1]}): for ax0_ax1_ax2_ax3_ax4_fused in T.serial(T.int64(48384)): with T.block("p0_global.vtcm"): ... for ax0_ax1_ax2_ax3_ax4_ax5_ax6_fused in T.serial(T.int64(3072)): with T.block("fused_constant_global.vtcm"): ... ``` * Disable parallelization, since doing `dma_copy` under a parallel loop is not supported by the current Hexagon runtime. -- This is an automated message from the Apache Git Service. To respond to the message, please log on to GitHub and use the URL above to go to the specific comment. To unsubscribe, e-mail: [email protected] For queries about this service, please contact Infrastructure at: [email protected]
