This is an automated email from the ASF dual-hosted git repository.
github-bot pushed a change to branch nightly
in repository https://gitbox.apache.org/repos/asf/tvm.git
from fc2a9e50af [CODEGEN][METAL] Fix unaligned vector load (#14332)
add c6c89c3a25 [Hexagon] Add concept of DMA groups (#14254)
add 06276846a1 [Docs] Update listed tvmc python dependencies (#14341)
add 36b30974a9 [MetaSchedule] Introducing MemHammer (#14164)
No new revisions were added by this update.
Summary of changes:
docs/install/from_source.rst | 2 +-
include/tvm/meta_schedule/postproc.h | 3 +-
include/tvm/tir/builtin.h | 37 +-
include/tvm/tir/schedule/schedule.h | 5 +
include/tvm/tir/stmt.h | 31 +
include/tvm/tir/transform.h | 6 +
.../postproc/disallow_async_strided_mem_copy.py | 11 +-
python/tvm/tir/schedule/schedule.py | 24 +
python/tvm/tir/tensor_intrin/hexagon.py | 35 +-
python/tvm/tir/transform/transform.py | 11 +
src/driver/driver_api.cc | 2 +-
.../feature_extractor/per_store_feature.cc | 1 +
.../postproc/disallow_async_strided_mem_copy.cc | 8 +-
src/meta_schedule/postproc/verify_gpu_code.cc | 1 +
src/runtime/hexagon/hexagon_device_api.cc | 19 +-
src/runtime/hexagon/hexagon_user_dma.cc | 14 +-
src/runtime/hexagon/hexagon_user_dma.h | 31 +-
src/runtime/hexagon/ring_buffer.h | 76 +-
src/tir/op/builtin.cc | 6 +
src/tir/schedule/concrete_schedule.cc | 24 +
src/tir/schedule/concrete_schedule.h | 5 +
src/tir/schedule/primitive.h | 9 +
src/tir/schedule/primitive/read_write_at.cc | 421 ++++++++
src/tir/schedule/schedule.cc | 4 +
src/tir/schedule/traced_schedule.cc | 28 +
src/tir/schedule/traced_schedule.h | 5 +
src/tir/transforms/inject_software_pipeline.cc | 35 +-
src/tir/transforms/lower_async_dma.cc | 172 ++--
src/tir/transforms/lower_tvm_builtin.cc | 26 +
src/tir/transforms/memhammer_coalesce.cc | 234 +++++
src/tir/transforms/memhammer_intermediate_stage.cc | 444 ++++++++
src/tir/transforms/memhammer_lower_auto_copy.cc | 779 ++++++++++++++
src/tir/transforms/memhammer_rewrite_rule.h | 242 +++++
src/tir/transforms/memhammer_tensorcore_rewrite.cc | 350 +++++++
.../cpp-runtime/hexagon/hexagon_user_dma_tests.cc | 2 +-
tests/cpp-runtime/hexagon/ring_buffer_tests.cc | 203 +++-
.../metaschedule_e2e/test_resnet50_int8.py | 1 -
.../test_hexagon/test_async_dma_pipeline.py | 6 +-
.../test_hexagon/test_software_pipeline_async.py | 1 -
...test_tir_transform_memhammer_lower_auto_copy.py | 1062 ++++++++++++++++++++
40 files changed, 4176 insertions(+), 200 deletions(-)
create mode 100644 src/tir/schedule/primitive/read_write_at.cc
create mode 100644 src/tir/transforms/memhammer_coalesce.cc
create mode 100644 src/tir/transforms/memhammer_intermediate_stage.cc
create mode 100644 src/tir/transforms/memhammer_lower_auto_copy.cc
create mode 100644 src/tir/transforms/memhammer_rewrite_rule.h
create mode 100644 src/tir/transforms/memhammer_tensorcore_rewrite.cc
create mode 100644
tests/python/unittest/test_tir_transform_memhammer_lower_auto_copy.py
