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from 7831a79f7f [Hexagon] Fix deprecated call for data layout size in bits
(#14438)
add b724c87f76 [MetaSchedule][ARM] Enable ARM CPU intrinsic for
MetaSchedule (#14209)
add 98007f90d8 [Relay] Move pad value extraction past null pointer check
(#14445)
add 49e6695586 [CI] Add llvm-15 and mlir-15 to Docker setup (#14303)
No new revisions were added by this update.
Summary of changes:
docker/Dockerfile.ci_cpu | 3 +
docker/install/ubuntu_install_llvm_from_source.sh | 1 +
include/tvm/meta_schedule/schedule_rule.h | 2 +
include/tvm/runtime/container/array.h | 43 ++++++++++
python/tvm/tir/tensor_intrin/arm_cpu.py | 99 ++++++++++++++--------
src/meta_schedule/schedule_rule/schedule_rule.cc | 90 ++++++++++++++++++++
.../space_generator/space_generator.cc | 19 +++++
src/relay/transforms/fold_explicit_padding.cc | 2 +-
.../test_meta_schedule_post_order_apply.py | 73 ++++++++++++++++
9 files changed, 296 insertions(+), 36 deletions(-)
