Hzfengsy commented on code in PR #14766:
URL: https://github.com/apache/tvm/pull/14766#discussion_r1186976209
##########
tests/python/unittest/test_meta_schedule_schedule_rule_mlt_tc.py:
##########
@@ -988,15 +988,15 @@ def conv2d_1x1_0(inputs: T.Buffer((1, 16, 16, 64),
"float16"), weight: T.Buffer(
v2, v3 = T.axis.remap("SS", [ax2_1, ax3])
v4_o = T.axis.spatial(1, 0)
v5_o = T.axis.spatial(1, 0)
-
T.reads(conv2d_nhwc_reindex_shared_wmma_accumulator[v0, v1, v2, v3, 0:16, 0:16])
- T.writes(conv2d_nhwc_reindex_shared[v0, v1,
v2, v3, 0:16, 0:16])
+
T.reads(conv2d_nhwc_reindex_shared_wmma_accumulator[v0, v1, 0, 0, 0:16, 0:16])
Review Comment:
I think this kind of chengs may break current tensorcore support IMO. cc
@junrushao @vinx13
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