I've done several searches on the wiki and I can't seem to find any block diagram of the Freerunner hardware. Is there any such thing? It would sure help to clarify how all this stuff is connected.
---------- Forwarded message ---------- > From: Andy Green <[EMAIL PROTECTED]> > Date: Thu, 05 Jun 2008 09:29:36 +0100 > Subject: Re: Yummy new CPU/GPU combo ... > We would rightly deserve to get our asses laughed at if we did that. > You're likely thinking about the actual SD Card interface is now via the > Glamo, which has an SD interface poking out of it. WIFI is hooked to > the CPU SDIO bus and we don't otherwise use these buses. > > | If it's connected to the address/data bus, why is it so slow and why > can't > | DMA be used to copy data to it? > > DMA can be used, I seem to recall someone saying they did something with > it in Xglamo, but PIO isn't where the problems are coming from. > > The Glamo offers normal async memory bus interface which we use, but it > has a bunch of timing constraints. (There is a synchronous burst bus > mode that we don't use because the CPU doesn't support it and adding a > CPLD in there to translate will eat power and doesn't make sense.) >
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