On Mon, 24 Aug 2026 07:06:07 GMT, Jatin Bhateja <[email protected]> wrote:
>> Hi @jatin-bhateja,
>>
>> `compiler/vectorapi/TestFloat16VectorFMAAccumSpill.java` fails
>> deterministically in our downstream CI on a Sapphire Rapids host
>> (avx512_fp16, linux-x64 fastdebug, master @ 241381ba70496).
>>
>> [2026-08-18T02:43:54.226Z] Failed IR Rules (1) of Methods (1)
>> [2026-08-18T02:43:54.226Z] ----------------------------------
>> [2026-08-18T02:43:54.226Z] 1) Method
>> "compiler.vectorapi.TestFloat16VectorFMAAccumSpill::fmaAccum" - [Failed IR
>> rules: 1]:
>> [2026-08-18T02:43:54.226Z] * @IR rule 2:
>> "@compiler.lib.ir_framework.IR(phase={FINAL_CODE}, applyIfCPUFeatureAnd={},
>> applyIfPlatformAnd={}, applyIf={}, applyIfCPUFeatureOr={},
>> applyIfCPUFeature={"avx512_fp16", "true"}, counts={},
>> failOn={"_#C#MEM_TO_REG_SPILL_COPY_TYPE#_", "vector[xyz]"}, applyIfAnd={},
>> applyIfPlatform={}, applyIfPlatformOr={}, applyIfOr={})"
>> [2026-08-18T02:43:54.226Z] > Phase "Final Code":
>> [2026-08-18T02:43:54.226Z] - failOn: Graph contains forbidden nodes:
>> [2026-08-18T02:43:54.227Z] * Constraint 1:
>> "(\d+(\s){2}(MemToRegSpillCopy.*)+(\s){2}===.*vector[xyz].*)"
>> [2026-08-18T02:43:54.227Z] - Matched forbidden nodes (8):
>> [2026-08-18T02:43:54.227Z] * 6394 MemToRegSpillCopy === _
>> 1139 [[ 1138 ]] vectorz<S,32> !jvms: Float16Vector::lanewiseTemplate @
>> bci:70 (line 1112) Float16Vector512::lanewise @ bci:4 (line 318)
>> Float16Vector512::lanewise @ bci:4 (line 42)
>> TestFloat16VectorFMAAccumSpill::fmaAccum @ bci:582 (line 131)
>> [2026-08-18T02:43:54.227Z] * 6510 MemToRegSpillCopy === _
>> 1130 [[ 1129 ]] vectorz<S,32> !jvms: Float16Vector::lanewiseTemplate @
>> bci:70 (line 1112) Float16Vector512::lanewise @ bci:4 (line 318)
>> Float16Vector512::lanewise @ bci:4 (line 42)
>> TestFloat16VectorFMAAccumSpill::fmaAccum @ bci:582 (line 131)
>> [2026-08-18T02:43:54.227Z] * 6630 MemToRegSpillCopy === _
>> 1121 [[ 1120 ]] vectorz<S,32> !jvms: Float16Vector::lanewiseTemplate @
>> bci:70 (line 1112) Float16Vector512::lanewise @ bci:4 (line 318)
>> Float16Vector512::lanewise @ bci:4 (line 42)
>> TestFloat16VectorFMAAccumSpill::fmaAccum @ bci:582 (line 131)
>> [2026-08-18T02:43:54.227Z] * 6754 MemToRegSpillCopy === _
>> 1112 [[ 1111 ]] vectorz<S,32> !jvms: Float16Vector::lanewiseTemplate @
>> bci:70 (line 1112) Float16Vector512::lanewise @ bci:4 (line 318)
>> Float16Vector512::lanewise @ bci:4 (line 42)
>> TestFloat16VectorFMAAccumSpill::fmaAccum @ bci:582 (line 131)
>> [2026-08-18T02:43:54.228Z] * 6882 MemToRegSpillCo...
>
> Hi @erifan , Test delicately checks for non existence of spills
> (MachSpillCopyNode) IR, with -ea -esa additional assertions gets enabled
> which can increase the register pressure leading to extra spills, I think you
> can file a test bug JBS for this.
>
> I confirm that test passes in default mode, but fails with -ea -esa (may be
> we need to ProblemList it with -ea -esa).
@jatin-bhateja https://bugs.openjdk.org/browse/JDK-8390927
-------------
PR Comment: https://git.openjdk.org/jdk/pull/31724#issuecomment-5392196507
