Dear coreboot readers! This is the automated build check service of coreboot.
The developer "hailfinger" checked in revision 3061 to the coreboot source repository and caused the following changes: Change Log: Support SPI flash chips bigger than 512 kByte sitting behind IT8716F Super I/O performing LPC-to-SPI flash translation. Signed-off-by: Ronald Hoogenboom <[EMAIL PROTECTED]> Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Build Log: Compilation of amd:serengeti_cheetah_fam10 is still broken See the error log at http://qa.linuxbios.org/log_buildbrd.php?revision=3061&device=serengeti_cheetah_fam10&vendor=amd If something broke during this checkin please be a pain in hailfinger's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
