-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 > I'm not sure I understand what you mean. Check the contents of the > registers 0xe4 0xe5 0x5b 0x58 0x53 0x95 0x94 of the PCI device 00:11.0 > (using lspci -xxx)? If yes, see below.
Yes. Those are multifunction pin config, mostly platform specific (desktop/notebook) so this is not in motherboard code but in generic VT8237R code. >> 0:11.0 0xe4 0xe5 0x5b 0x58 0x53 0x95 0x94 > || || || || || || || > values: 0x04 0x09 0x0b 0x43 0x00 0xcc 0xa4 > I don't understand. Match what? Ok I checked now and it matches what is programmed in Coreboot. >> Regarding the SIO configuration just one bit >> is different - GPIO2 bit 4. Please try to change chipset voltage in BIOS >> and see if it changes too. > > Yes, when changing the BIOS default of 1.5V to 1.6V I get this > superiotool diff: > > LDN 0x09 (GPIO 2, GPIO 3, GPIO 4, GPIO 5, SUSLED) > idx 30 e0 e1 e2 e3 e4 e5 f0 f1 f2 f3 f4 f5 f6 f7 > -val 09 de 01 00 03 b4 00 ff ff ff 09 ff ff ff ff > +val 09 de 01 00 03 a4 00 ff ff ff 09 ff ff ff ff > def 00 ff 00 00 ff 00 00 ff 00 00 00 ff 00 00 00 > > So yes, it's indeed GPIO2 bit 4. Hmm I checked my test dumps and I have 0xa4 for 1.6V and 0xb4 for the 1.5V. So I must conclude I made a default 1.6V instead of 1.5V by mistake ;) But the documentation on wiki is correct: 1 = 1.5V Chipset voltage 0 = 1.6V Chipset voltage I think you can now continue with Coreboot there. The clock chip should be strapped default to something reasonable - 200MHz #i2cget 0 0x69 0x0 w 0x620f 0xf is number of registers, 0x62 means 2 = 200 MHz 6 = PLL1 PLL2 spread spectrum enable. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFHkywO3J9wPJqZRNURAjvbAKCJo6CBuGgyg5fBZZx/ORfWBEdufQCeJCtB WZFe1Yt+kc35Qq5y84LrCSU= =ZJ95 -----END PGP SIGNATURE----- -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
