Peter Stuge napsal(a): > On Sun, Jan 27, 2008 at 01:51:15PM +0100, Rudolf Marek wrote: >> The logical device for SPI flash has only bit 1 for enable/disable. >> Bit 0 is reserved. > > I guess bit 3 also reserved?
Yes all others are reserved too. >> Question is how to solve that? Would help to ommit 2e.9 off/on in >> Config.lb? And enable this manually in sio_init in MB specific >> setup? > > Is this MB-specific? It sounds like it's superio-specific, in which > case I guess the superio code should take care of not trashing the > register. Well yes, it is superio specific. They simply overloaded one logical device with more "subdevices". I dont know how to fit this into PNP model. The best would be to ignore this logical device in PNP system config at all and handle the programming in MB specific code. This problem is more general and not MB specific. I can't even fix the code not trashing just whole register. For example the enable for SPI flash is at bit 1 and not bit0, so the generic code can't be used at all. In my case I need bits 0 and 4 set, so fixing the generic code to handle just bit0 would work for me, but not in general - like the SPI logical device. I hope it is more clear now. Imho datasheet at 0x30 says it all ;) Thanks, Rudolf Thanks, Rudolf -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
