Author: rminnich
Date: 2008-02-01 21:35:53 +0100 (Fri, 01 Feb 2008)
New Revision: 571
Added:
coreboot-v3/northbridge/amd/geodelx/apic
coreboot-v3/northbridge/amd/geodelx/domain
coreboot-v3/northbridge/amd/geodelx/pci
Removed:
coreboot-v3/northbridge/amd/geodelx/dts
Modified:
coreboot-v3/device/device.c
coreboot-v3/device/pci_device.c
coreboot-v3/mainboard/pcengines/alix1c/dts
coreboot-v3/northbridge/amd/geodelx/geodelx.c
coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
coreboot-v3/util/dtc/flattree.c
Log:
with VSA operating correctly. This is tested with AMD's recently
released new-model VSA code.
Changes:
Index: util/dtc/flattree.c
Add an ID entry for apic properties.
Index: northbridge/amd/geodelx/apic
This is a new dts for the northbridge used as an APIC.
Index: northbridge/amd/geodelx/pci
This is a new dts for the northbridge used as a PCI device.
Index: northbridge/amd/geodelx/geodelx.c
Fix a non-obvious bug: we had set phase3 scan bus for both the
domain AND the PCI device, which is a mistake: can't scan from the
PCI device too.
Index: northbridge/amd/geodelx/domain
This is a new dts for the northbridge used as an pci domain.
Created via svn move dts domain
Index: device/pci_device.c
If there are leftover devices, it is now a warning, not an error,
since there are
some no-pci devices in the tree now. For future: only complain about
leftover PCI devices ...
Index: device/device.c
make devcnt a global and initialize it in init_dev. Add a debug printk.
Index: mainboard/pcengines/alix1c/dts
Add an 'apic' entry for the mainboard. This actually looks pretty clean
to me, the way it went in.
Index: northbridge/amd/geodelx/vsmsetup.c
Delete all pcibios int support, no longer needed for VSA.
Please note that this patch includes Carl-Daniel's improvements
below, which I have Ack-ed.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
A few minor comments. It would be great if you could address them before
committing.
northbridge/amd/geodelx/domain is a copy of northbridge/amd/geodelx/dts.
You probably want to use "svn mv" for that because it preserves history
and the old file was probably intended to have been moved, not copied.
northbridge/amd/geodelx/vsmsetup.c:247: warning:
?\226?\128?\152biosint?\226?\128?\153 defined but
not used
Since the new VSA does not use BIOSINT services anymore, deleting
biosint and related functions from vsmsetup.c would shrink vsmsetup.c by
one fourth. Patch follows (could you merge it into your patch?):
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3/device/device.c 2008-01-31 14:01:23 UTC (rev 570)
+++ coreboot-v3/device/device.c 2008-02-01 20:35:53 UTC (rev 571)
@@ -67,6 +67,12 @@
static struct device devs[MAX_DEVICES];
/**
+ * the number of devices that have been allocated
+ */
+static int devcnt;
+
+
+/**
* The device creator.
*
* reserves a piece of memory for a device in the tree
@@ -76,9 +82,9 @@
static struct device *new_device(void)
{
- static int devcnt=0;
devcnt++;
+ printk(BIOS_SPEW, "%s: devcnt %d\n", __FUNCTION__, devcnt);
/* Should we really die here? */
if (devcnt>=MAX_DEVICES) {
die("Too many devices. Increase MAX_DEVICES\n");
@@ -155,6 +161,7 @@
dev->ops = c->ops;
last_dev_p = &dev->next;
}
+ devcnt = 0;
}
/**
Modified: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3/device/pci_device.c 2008-01-31 14:01:23 UTC (rev 570)
+++ coreboot-v3/device/pci_device.c 2008-02-01 20:35:53 UTC (rev 571)
@@ -1136,9 +1136,9 @@
if (old_devices) {
struct device *left;
for (left = old_devices; left; left = left->sibling) {
- printk(BIOS_ERR, "%s\n", dev_path(left));
+ printk(BIOS_SPEW, "%s\n", left->dtsname);
}
- die("PCI: Left over static devices.\n");
+ banner(BIOS_SPEW, "PCI: Left over static devices.\n");
}
/* For all children that implement scan_bus() (i.e. bridges)
Modified: coreboot-v3/mainboard/pcengines/alix1c/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-01-31 14:01:23 UTC (rev
570)
+++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-02-01 20:35:53 UTC (rev
571)
@@ -25,11 +25,16 @@
cpus {
enabled;
};
+ apic {
+ /config/("northbridge/amd/geodelx/apic");
+ enabled;
+ };
domain0 {
- /config/("northbridge/amd/geodelx/dts");
+ /config/("northbridge/amd/geodelx/domain");
enabled;
pcidomain = "0";
device0,0 {
+ /config/("northbridge/amd/geodelx/pci");
enabled;
pcipath = "1,0";
};
Added: coreboot-v3/northbridge/amd/geodelx/apic
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/apic (rev 0)
+++ coreboot-v3/northbridge/amd/geodelx/apic 2008-02-01 20:35:53 UTC (rev
571)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ constructor = "geodelx_north_constructors";
+ apicid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+};
+
Copied: coreboot-v3/northbridge/amd/geodelx/domain (from rev 570,
coreboot-v3/northbridge/amd/geodelx/dts)
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/domain (rev 0)
+++ coreboot-v3/northbridge/amd/geodelx/domain 2008-02-01 20:35:53 UTC (rev
571)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ constructor = "geodelx_north_constructors";
+ domainid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+};
+
Deleted: coreboot-v3/northbridge/amd/geodelx/dts
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/dts 2008-01-31 14:01:23 UTC (rev
570)
+++ coreboot-v3/northbridge/amd/geodelx/dts 2008-02-01 20:35:53 UTC (rev
571)
@@ -1,25 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2008 Ronald G. Minnich <[EMAIL PROTECTED]>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-{
- constructor = "geodelx_north_constructors";
- domainid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
-};
-
Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-01-31 14:01:23 UTC
(rev 570)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-02-01 20:35:53 UTC
(rev 571)
@@ -380,9 +380,12 @@
};
/** Operations for when the northbridge is running a PCI device. */
+/** Note that phase3 scan is done in the domain,
+ * and MUST NOT be done here too
+ */
static struct device_operations geodelx_pci_ops = {
.constructor = default_device_constructor,
- .phase3_scan = pci_domain_scan_bus,
+ .phase3_scan = 0,
.phase4_read_resources = pci_domain_read_resources,
.phase4_set_resources = geodelx_northbridge_set_resources,
.phase5_enable_resources = enable_childrens_resources,
Added: coreboot-v3/northbridge/amd/geodelx/pci
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/pci (rev 0)
+++ coreboot-v3/northbridge/amd/geodelx/pci 2008-02-01 20:35:53 UTC (rev
571)
@@ -0,0 +1,25 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+{
+ constructor = "geodelx_north_constructors";
+ pciid = "PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LXBRIDGE";
+};
+
Modified: coreboot-v3/northbridge/amd/geodelx/vsmsetup.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-01-31 14:01:23 UTC
(rev 570)
+++ coreboot-v3/northbridge/amd/geodelx/vsmsetup.c 2008-02-01 20:35:53 UTC
(rev 571)
@@ -222,88 +222,3 @@
"do_vsmbios: VSA2 VR signature not valid, install
failed!\n");
}
-enum {
- PCIBIOS = 0x1a,
- MEMSIZE = 0x12
-};
-
-int pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
- unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
- unsigned long *pecx, unsigned long *peax, unsigned long *pflags);
-
-int handleint21(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
- unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
- unsigned long *pecx, unsigned long *peax,
- unsigned long *pflags);
-
-/* see the vga_exit() call. until we clean this up this function will remain
here */
-static int biosint(unsigned long intnumber,
- unsigned long gsfs, unsigned long dses,
- unsigned long edi, unsigned long esi,
- unsigned long ebp, unsigned long esp,
- unsigned long ebx, unsigned long edx,
- unsigned long ecx, unsigned long eax,
- unsigned long cs_ip, unsigned short stackflags)
-{
- unsigned long ip;
- unsigned long cs;
- unsigned long flags;
- int ret = -1;
-
- ip = cs_ip & 0xffff;
- cs = cs_ip >> 16;
- flags = stackflags;
-
- printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
- printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
- eax, ebx, ecx, edx);
- printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
- ebp, esp, edi, esi);
- printk(BIOS_DEBUG, "biosint: ip 0x%lx cs 0x%lx flags 0x%lx\n",
- ip, cs, flags);
- printk(BIOS_DEBUG, "biosint: gs 0x%lx fs 0x%lx ds 0x%lx es 0x%lx\n",
- gsfs >> 16, gsfs & 0xffff, dses >> 16, dses & 0xffff);
-
- // cases in a good compiler are just as good as your own tables.
- switch (intnumber) {
- case 0 ... 15:
- // These are not BIOS service, but the CPU-generated exceptions
- printk(BIOS_INFO, "biosint: Oops, exception %lu\n", intnumber);
- if (esp < 0x1000) {
- printk(BIOS_DEBUG, "Stack contents: ");
- while (esp < 0x1000) {
- printk(BIOS_DEBUG, "0x%04x ", *(unsigned short
*)esp);
- esp += 2;
- }
- printk(BIOS_DEBUG, "\n");
- }
- printk(BIOS_DEBUG, "biosint: Bailing out ... not now\n");
- // "longjmp"
- //vga_exit();
- break;
-
- case PCIBIOS:
- ret = pcibios(&edi, &esi, &ebp, &esp,
- &ebx, &edx, &ecx, &eax, &flags);
- break;
- case MEMSIZE:
- // who cares.
- eax = 128 * 1024;
- ret = 0;
- break;
- case 0x15:
- ret = handleint21(&edi, &esi, &ebp, &esp,
- &ebx, &edx, &ecx, &eax, &flags);
- break;
- default:
- printk(BIOS_INFO, "BIOSINT: Unsupport int #0x%lx\n", intnumber);
- break;
- }
- if (ret)
- flags |= 1; // carry flags
- else
- flags &= ~1;
- stackflags = flags;
- return ret;
-}
-
Modified: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3/util/dtc/flattree.c 2008-01-31 14:01:23 UTC (rev 570)
+++ coreboot-v3/util/dtc/flattree.c 2008-02-01 20:35:53 UTC (rev 571)
@@ -551,6 +551,10 @@
fprintf(f, "\t.id =
{.type=DEVICE_ID_PCI,.u={.pci={ %s }}},\n",
prop->val.val);
}
+ if (streq(prop->name, "apicid")){
+ fprintf(f, "\t.id =
{.type=DEVICE_ID_APIC,.u={.pci={ %s }}},\n",
+ prop->val.val);
+ }
}
}
/* Process the properties specified in the mainboard dts.
--
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