Hello,
Attached a bios-size patch for the latest qemu version 0.9.1.
This should be applied instead of the 0.9.0 patches that appear in the qemu
tutorial <http://www.coreboot.org/QEMU_Build_Tutorial#Building_Qemu>.
Haven't testes it throughly but it worked for me to run coreboot + ADLO + my
system.
Cheers, Reuven
diff -Naur ./qemu-0.9.1.orig/hw/pc.c ./qemu-0.9.1.patched/hw/pc.c
--- ./qemu-0.9.1.orig/hw/pc.c 2008-01-06 21:38:42.000000000 +0200
+++ ./qemu-0.9.1.patched/hw/pc.c 2008-02-15 09:58:36.000000000 +0200
@@ -794,15 +794,13 @@
cpu_register_physical_memory(0xc0000, 0x10000,
vga_bios_offset | IO_MEM_ROM);
- /* map the last 128KB of the BIOS in ISA space */
+ /* copy the last 128KB of the BIOS to ISA space */
isa_bios_size = bios_size;
if (isa_bios_size > (128 * 1024))
isa_bios_size = 128 * 1024;
- cpu_register_physical_memory(0xd0000, (192 * 1024) - isa_bios_size,
- IO_MEM_UNASSIGNED);
- cpu_register_physical_memory(0x100000 - isa_bios_size,
- isa_bios_size,
- (bios_offset + bios_size - isa_bios_size) | IO_MEM_ROM);
+ memcpy(phys_ram_base + 0x100000 - isa_bios_size,
+ phys_ram_base + bios_offset + bios_size - isa_bios_size,
+ isa_bios_size);
{
ram_addr_t option_rom_offset;
@@ -846,7 +844,7 @@
ferr_irq = i8259[13];
if (pci_enabled) {
- pci_bus = i440fx_init(&i440fx_state, i8259);
+ pci_bus = i440fx_init(&i440fx_state, i8259, ram_size);
piix3_devfn = piix3_init(pci_bus, -1);
} else {
pci_bus = NULL;
diff -Naur ./qemu-0.9.1.orig/hw/pc.h ./qemu-0.9.1.patched/hw/pc.h
--- ./qemu-0.9.1.orig/hw/pc.h 2008-01-06 21:38:42.000000000 +0200
+++ ./qemu-0.9.1.patched/hw/pc.h 2008-02-15 10:16:27.000000000 +0200
@@ -97,7 +97,7 @@
int pcspk_audio_init(AudioState *, qemu_irq *pic);
/* piix_pci.c */
-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
+PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic, int ram_size);
void i440fx_set_smm(PCIDevice *d, int val);
int piix3_init(PCIBus *bus, int devfn);
void i440fx_init_memory_mappings(PCIDevice *d);
diff -Naur ./qemu-0.9.1.orig/hw/piix_pci.c ./qemu-0.9.1.patched/hw/piix_pci.c
--- ./qemu-0.9.1.orig/hw/piix_pci.c 2008-01-06 21:38:42.000000000 +0200
+++ ./qemu-0.9.1.patched/hw/piix_pci.c 2008-02-15 10:20:00.000000000 +0200
@@ -169,7 +169,7 @@
return 0;
}
-PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic)
+PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic, int ram_size)
{
PCIBus *b;
PCIDevice *d;
@@ -200,6 +200,10 @@
d->config[0x0a] = 0x00; // class_sub = host2pci
d->config[0x0b] = 0x06; // class_base = PCI_bridge
d->config[0x0e] = 0x00; // header_type
+ ram_size = ram_size / 8 / 1024 / 1024;
+ if (ram_size > 255)
+ ram_size = 255;
+ d->config[0x57] = ram_size;
d->config[0x72] = 0x02; /* SMRAM */
--
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