Hello,
Ühel kenal päeval, R, 2008-02-08 kell 17:54, kirjutas Mart Raudsepp:
>
> * Add a field to the struct (either treated as boolean, or a flag),
> that
> tells the logic if this entry should be considered in the
> auto-detection
> logic or skipped
> Pros:
> * can skip boards from PCI based auto-detection logic, requiring
> user specifying it;
> * has safeguards still in place (in this specific case will allow
> to
> claim it's a DBE61 only on Geode based products)
> Potential cons: extra struct field
As there have been no replies on mailing list on this, I went ahead and
made a simple patch for the above quoted approach. I remember that using
an extra field was found to be the preferred approach by several people
on IRC as well.
Attached you will find that patch, plus an accordingly modified
DBE61/DBE62 board enable patch.
Comments or Acks? :)
Mart Raudsepp,
Software Engineer,
Artec Design LLC
commit d41c7bd40cccd6c6ca3951d6aa2b0ae02801a2e7
Author: Mart Raudsepp <[EMAIL PROTECTED]>
Date: Mon Feb 18 15:32:29 2008 +0200
flashrom: Add possibility to skip board entries from auto-detection logic
Add a flag field to board_pciid_enable struct, currently with bit0 as BOARD_FLAGS_NO_AUTO.
Skip board entries with BOARD_FLAGS_NO_AUTO flag in the auto-detection loop in board_match_pci_card_ids().
Signed-off-by: Mart Raudsepp <[EMAIL PROTECTED]>
diff --git a/board_enable.c b/board_enable.c
index 907774d..084e248 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -396,38 +396,39 @@ struct board_pciid_enable {
const char *name;
int (*enable) (const char *name);
+ int flags;
};
struct board_pciid_enable board_pciid_enables[] = {
{0x10de, 0x0360, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- "gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash},
+ "gigabyte", "m57sli", "GIGABYTE GA-M57SLI-S4", it87xx_probe_spi_flash, 0},
{0x10de, 0x03e0, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- "gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash},
+ "gigabyte", "m61p", "GIGABYTE GA-M61P-S3", it87xx_probe_spi_flash, 0},
{0x1039, 0x0761, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- "gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK", it87xx_probe_spi_flash},
+ "gigabyte", "2761gxdk", "GIGABYTE GA-2761GXDK", it87xx_probe_spi_flash, 0},
{0x1022, 0x7468, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e},
+ "iwill", "dk8_htx", "IWILL DK8-HTX", w83627hf_gpio24_raise_2e, 0},
{0x10de, 0x005e, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
- "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e},
+ "msi", "k8n-neo3", "MSI K8N Neo3", w83627thf_gpio4_4_raise_4e, 0},
{0x1022, 0x746B, 0x1022, 0x36C0, 0x0000, 0x0000, 0x0000, 0x0000,
- "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e},
+ "AGAMI", "ARUMA", "agami Aruma", w83627hf_gpio24_raise_2e, 0},
{0x1106, 0x3177, 0x1106, 0xAA01, 0x1106, 0x3123, 0x1106, 0xAA01,
- NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m},
+ NULL, NULL, "VIA EPIA M/MII/...", board_via_epia_m, 0},
{0x1106, 0x3177, 0x1043, 0x80A1, 0x1106, 0x3205, 0x1043, 0x8118,
- NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx},
+ NULL, NULL, "ASUS A7V8-MX SE", board_asus_a7v8x_mx, 0},
{0x1106, 0x3227, 0x1106, 0xAA01, 0x1106, 0x0259, 0x1106, 0xAA01,
- NULL, NULL, "VIA EPIA SP", board_via_epia_sp},
+ NULL, NULL, "VIA EPIA SP", board_via_epia_sp, 0},
{0x8086, 0x1076, 0x8086, 0x1176, 0x1106, 0x3059, 0x10f1, 0x2498,
- NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx},
+ NULL, NULL, "Tyan Tomcat K7M", board_asus_a7v8x_mx, 0},
{0x10B9, 0x1541, 0x0000, 0x0000, 0x10B9, 0x1533, 0x0000, 0x0000,
- "asus", "p5a", "ASUS P5A", board_asus_p5a},
+ "asus", "p5a", "ASUS P5A", board_asus_p5a, 0},
{0x1166, 0x0205, 0x1014, 0x0347, 0x0000, 0x0000, 0x0000, 0x0000,
- "ibm", "x3455", "IBM x3455", board_ibm_x3455},
+ "ibm", "x3455", "IBM x3455", board_ibm_x3455, 0},
{0x8086, 0x7110, 0x0000, 0x0000, 0x8086, 0x7190, 0x0000, 0x0000,
- "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3},
+ "epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3, 0},
{0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33,
- "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd},
- {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL} /* Keep this */
+ "acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd, 0},
+ {0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, 0} /* Keep this */
};
/**
@@ -487,6 +488,10 @@ static struct board_pciid_enable *board_match_pci_card_ids(void)
if (!board->first_card_vendor || !board->first_card_device)
continue;
+ /* If no_auto is set, then don't consider this entry in auto-detection */
+ if (board->flags & BOARD_FLAGS_NO_AUTO)
+ continue;
+
if (!pci_card_find(board->first_vendor, board->first_device,
board->first_card_vendor,
board->first_card_device))
diff --git a/flash.h b/flash.h
index 67d276f..7d10cad 100644
--- a/flash.h
+++ b/flash.h
@@ -290,6 +290,8 @@ struct pci_dev *pci_card_find(uint16_t vendor, uint16_t device,
/* board_enable.c */
int board_flash_enable(const char *vendor, const char *part);
+#define BOARD_FLAGS_NO_AUTO 0x01 /* don't check this board in PCI ID based autodetection */
+
/* chipset_enable.c */
int chipset_flash_enable(void);
commit 633c8219c8504e796bfad7fc19dd3dffc3069325
Author: Mart Raudsepp <[EMAIL PROTECTED]>
Date: Mon Feb 18 15:33:10 2008 +0200
Add board_enable for Artec Group DBE61 and DBE62
Signed-off-by: Mart Raudsepp <[EMAIL PROTECTED]>
diff --git a/board_enable.c b/board_enable.c
index 084e248..3369125 100644
--- a/board_enable.c
+++ b/board_enable.c
@@ -28,6 +28,7 @@
#include <pci/pci.h>
#include <stdint.h>
#include <string.h>
+#include <fcntl.h>
#include "flash.h"
/*
@@ -368,6 +369,69 @@ static int board_acorp_6a815epd(const char *name)
}
/**
+ * Suited for Artec Group DBE61 and DBE62.
+ */
+static int board_artecgroup_dbe6x(const char *name)
+{
+#define DBE6x_MSR_DIVIL_BALL_OPTS 0x51400015
+#define DBE6x_PRI_BOOT_LOC_SHIFT (2)
+#define DBE6x_BOOT_OP_LATCHED_SHIFT (8)
+#define DBE6x_SEC_BOOT_LOC_SHIFT (10)
+#define DBE6x_PRI_BOOT_LOC (3 << DBE6x_PRI_BOOT_LOC_SHIFT)
+#define DBE6x_BOOT_OP_LATCHED (3 << DBE6x_BOOT_OP_LATCHED_SHIFT)
+#define DBE6x_SEC_BOOT_LOC (3 << DBE6x_SEC_BOOT_LOC_SHIFT)
+#define DBE6x_BOOT_LOC_FLASH (2)
+#define DBE6x_BOOT_LOC_FWHUB (3)
+
+ unsigned long msr[2];
+ int msr_fd;
+ unsigned long boot_loc;
+
+ msr_fd = open("/dev/cpu/0/msr", O_RDWR);
+ if (msr_fd == -1) {
+ perror("open /dev/cpu/0/msr");
+ return -1;
+ }
+
+ if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
+ perror("lseek");
+ close(msr_fd);
+ return -1;
+ }
+
+ if (read(msr_fd, (void*) msr, 8) != 8) {
+ perror("read");
+ close(msr_fd);
+ return -1;
+ }
+
+ if ((msr[0] & (DBE6x_BOOT_OP_LATCHED)) ==
+ (DBE6x_BOOT_LOC_FWHUB << DBE6x_BOOT_OP_LATCHED_SHIFT))
+ boot_loc = DBE6x_BOOT_LOC_FWHUB;
+ else
+ boot_loc = DBE6x_BOOT_LOC_FLASH;
+
+ msr[0] &= ~(DBE6x_PRI_BOOT_LOC | DBE6x_SEC_BOOT_LOC);
+ msr[0] |= ((boot_loc << DBE6x_PRI_BOOT_LOC_SHIFT) |
+ (boot_loc << DBE6x_SEC_BOOT_LOC_SHIFT));
+
+ if (lseek(msr_fd, DBE6x_MSR_DIVIL_BALL_OPTS, SEEK_SET) == -1) {
+ perror("lseek");
+ close(msr_fd);
+ return -1;
+ }
+
+ if (write(msr_fd, (void*) msr, 8) != 8) {
+ perror("write");
+ close(msr_fd);
+ return -1;
+ }
+
+ close(msr_fd);
+ return 0;
+}
+
+/**
* We use 2 sets of IDs here, you're free to choose which is which. This
* is to provide a very high degree of certainty when matching a board on
* the basis of subsystem/card IDs. As not every vendor handles
@@ -428,6 +492,10 @@ struct board_pciid_enable board_pciid_enables[] = {
"epox", "ep-bx3", "EPoX EP-BX3", board_epox_ep_bx3, 0},
{0x8086, 0x1130, 0x0000, 0x0000, 0x105a, 0x0d30, 0x105a, 0x4d33,
"acorp", "6a815epd", "Acorp 6A815EPD", board_acorp_6a815epd, 0},
+ {0x1022, 0x2090, 0x1022, 0x2090, 0x1022, 0x2080, 0x1022, 0x2080,
+ "artecgroup", "dbe61", "Artec Group DBE61", board_artecgroup_dbe6x, BOARD_FLAGS_NO_AUTO},
+ {0x1022, 0x2090, 0x1022, 0x2090, 0x1022, 0x2080, 0x1022, 0x2080,
+ "artecgroup", "dbe62", "Artec Group DBE62", board_artecgroup_dbe6x, BOARD_FLAGS_NO_AUTO},
{0, 0, 0, 0, 0, 0, 0, 0, NULL, NULL, 0} /* Keep this */
};
--
coreboot mailing list
[email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
