-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello all,
I'm trying to get the Asus M2V-MX SE working (K8T890/VT8237S) it has AM2 socket. CPU is semperon model 127 fam f Currently there is some problem with memory, I have attached the log. I have no clue what might be wrong. The module is 512MB 533MHz single DDR2 with CAS4. The FIDVID changing and fidvid setup is disabled, reset of HT is disabled. It seems to fall down the drain on very same place. Any clue? Maybe I have some options wrong? What should I check please? I checked I2C reading and they are correct (I verified with EEPROM dump) I dont understand why: ... Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB ... The range is only to 200MB ??? export MEM_TRAIN_SEQ:=0 I have no other DDR2 module to check. Thanks, Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFITYmF3J9wPJqZRNURAj/iAJ9wmNn9okVbF9Wn+xHNlTpfSBPrIQCfXqxG e8VpRhnd12QDnPFxg4jRSWk= =Sioj -----END PGP SIGNATURE-----
coreboot-2.0.0.0Fallback Po èen 9 21:25:28 CEST 2008 starting...
now booting... fallback
coreboot-2.0.0.0Normal Po èen 9 21:25:06 CEST 2008 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
now booting... Core0 started
started ap apicid:
SBLink=00
NC node|link=00
0001K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05
VIA HT caps: 0075
HT between CPU and NB OK, not requesting reset
0101ht reset -
NO reset
after smbus
after memreset
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Device error
Device error
Device error
Unbuffered
1 min_cycle_time:00000250
i:00000000
latencies:00000038
index:00000000
latency:00000003
value1:00000050
value2:00000500
new_cycle_time:00000500
new_latency:00000003
index:00000001
latency:00000004
value1:0000003d
value2:00000375
new_cycle_time:00000375
new_latency:00000004
index:00000002
latency:00000005
value1:0000003d
value2:00000375
new_cycle_time:00000375
new_latency:00000004
2 min_cycle_time:00000375
2 min_latency:00000004
3 min_cycle_time:00000375
3 min_latency:00000004
4 min_cycle_time:00000375
266Mhz
266Mhz
dimm socket: 00000000
trc
trcd
trrd
tras
update_dimm_Tras: 0 value=0000002d
update_dimm_Tras: 1 value=00000708
update_dimm_Tras: divisor=000000c8
update_dimm_Tras: clocks=00000009
trp
trtp
twr
tref
twtr
trfc
XRAM: 0x00080000 KB
Ram3
dimm_mask = 00000001
x4_mask = 00000000
x16_mask = 00000000
single_rank_mask = 00000001
ODC = 00111222
Addr Timing= 002f2f00
Initializing memory: done
sysinfo tom_k
00080000Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB
DQS Training:RcvrEn:Pass1: 00
train_DqsRcvrEn: begin ctrl 00000000
TrainRcvEn: 0 ctrl00000000
TrainRcvEn51: channel 00000000
TrainRcvEn52: index 00000010
TrainRcvEn53: TestAddr0B 00005000
TrainRcvEn541: RcvrEnDly 00000000
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = aa8aaaaa
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000000
TrainRcvEn56: RcvrEnDly 00000000
TrainRcvEn541: RcvrEnDly 00000001
QW0.lo : test_buf= fffb0bbc
value = 55555555
QW0.lo : addr_lo = 00500000
value = 55555555
QW0.hi : test_buf= fffb0bc0
value = 55555555
QW0.hi : addr_lo = 00500004
value = 55855555
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000001
TrainRcvEn56: RcvrEnDly 00000001
TrainRcvEn541: RcvrEnDly 00000002
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = a58aaaaa
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000002
TrainRcvEn56: RcvrEnDly 00000002
TrainRcvEn541: RcvrEnDly 00000003
QW0.lo : test_buf= fffb0bbc
value = 55555555
QW0.lo : addr_lo = 00500000
value = 55555555
QW0.hi : test_buf= fffb0bc0
value = 55555555
QW0.hi : addr_lo = 00500004
value = 55555555
TrainRcvEn542: Test0 00000000
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = aaaaaaaa
TrainRcvEn543: Test1 00000000
TrainRcvEn55: RcvrEnDly 00000003
TrainRcvEn61: RcvrEnDly 00000003
TrainRcvEn63: RcvrEnDly 00000003
TrainRcvEn64: CTLRMaxDelay 00000003
TrainRcvEn52: index 00000013
TrainRcvEn52: index 00000016
TrainRcvEn52: index 00000019
TrainRcvEn51: channel 00000001
TrainRcvEn52: index 00000010
TrainRcvEn52: index 00000013
TrainRcvEn52: index 00000016
TrainRcvEn52: index 00000019
TrainRcvEn65: CTLRMaxDelay 00000003
CTLRMaxDelay=03
train_DqsRcvrEn: end ctrl 00000000
done
DQS Training:DQSPos: 00
train_DqsPos: begin ctrl 00000000
TrainDQSRdWrPos: 0 ctrl 00000000
TrainDQSRdWrPos: 1 channel 00000000
TrainDQSRdWrPos: 21 DQSWrDelay 00000000
TrainReadPos00000000
TrainDQSPos begin 00000000
TrainDQSPos: 11 ChipSel 00000000
TrainDQSPos: 12 TestAddr 00001000
TrainDQSPos: 13 for read so write at
first00000000
TrainDQSPos: 141 DQSDelay 00000000
TrainDQSPos: 142 MutualCSPassW 000000ff
TrainDQSPos: 144 Pattern 00000000
TrainDQSPos: 145 MutualCSPassW 000000ff
test_buf= 000cea20 value =
00000000
taddr_lo = 00100000 value =
ffffefff
bitmap = 000000f0
test_buf= 000cea24 value =
00000000
taddr_lo = 00100004 value =
dfffdfff
bitmap = 00000000
test_buf= 000cea28 value =
ffffffff
taddr_lo = 00100008 value =
ffffefff
bitmap = 00000000
test_buf= 000cea2c value =
ffffffff
taddr_lo = 0010000c value =
dfffdfff
bitmap = 00000000
test_buf= 000cea30 value =
00000000
taddr_lo = 00100010 value =
ffffffff
bitmap = 00000000
test_buf= 000cea34 value =
00000000
taddr_lo = 00100014 value =
ffffffff
bitmap = 00000000
test_buf= 000cea38 value =
00000000
taddr_lo = 00100018 value =
00000000
bitmap = 00000000
test_buf= 000cea3c value =
00000000
taddr_lo = 0010001c value =
00000000
bitmap = 00000000
test_buf= 000cea40 value =
00000000
taddr_lo = 00100020 value =
00000000
bitmap = 00000000
test_buf= 000cea44 value =
00000000
taddr_lo = 00100024 value =
00000000
bitmap = 00000000
test_buf= 000cea48 value =
ffffffff
taddr_lo = 00100028 value =
ffffefff
bitmap = 00000000
test_buf= 000cea4c value =
ffffffff
taddr_lo = 0010002c value =
dfffdfdf
bitmap = 00000000
test_buf= 000cea50 value =
00000000
taddr_lo = 00100030 value =
ffffffff
bitmap = 00000000
test_buf= 000cea54 value =
00000000
taddr_lo = 00100034 value =
ffffffff
bitmap = 00000000
test_buf= 000cea58 value =
00000000
coreboot-2.0.0.0Fallback Po èen 9 21:25:28 CEST 2008 starting...
now booting... fallback
coreboot-2.0.0.0Normal Po èen 9 21:25:06 CEST 2008 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
now booting... Core0 started
started ap apicid:
SBLink=00
NC node|link=00
0001K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05
VIA HT caps: 0075
HT between CPU and NB OK, not requesting reset
0101ht reset -
NO reset
after smbus
after memreset
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Device error
Device error
Device error
Unbuffered
1 min_cycle_time:00000250
i:00000000
latencies:00000038
index:00000000
latency:00000003
value1:00000050
value2:00000500
new_cycle_time:00000500
new_latency:00000003
index:00000001
latency:00000004
value1:0000003d
value2:00000375
new_cycle_time:00000375
new_latency:00000004
index:00000002
latency:00000005
value1:0000003d
value2:00000375
new_cycle_time:00000375
new_latency:00000004
2 min_cycle_time:00000375
2 min_latency:00000004
3 min_cycle_time:00000375
3 min_latency:00000004
4 min_cycle_time:00000375
266Mhz
266Mhz
dimm socket: 00000000
trc
trcd
trrd
tras
update_dimm_Tras: 0 value=0000002d
update_dimm_Tras: 1 value=00000708
update_dimm_Tras: divisor=000000c8
update_dimm_Tras: clocks=00000009
trp
trtp
twr
tref
twtr
trfc
XRAM: 0x00080000 KB
Ram3
dimm_mask = 00000001
x4_mask = 00000000
x16_mask = 00000000
single_rank_mask = 00000001
ODC = 00111222
Addr Timing= 002f2f00
Initializing memory: done
sysinfo tom_k
00080000Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB
DQS Training:RcvrEn:Pass1: 00
train_DqsRcvrEn: begin ctrl 00000000
TrainRcvEn: 0 ctrl00000000
TrainRcvEn51: channel 00000000
TrainRcvEn52: index 00000010
TrainRcvEn53: TestAddr0B 00005000
TrainRcvEn541: RcvrEnDly 00000000
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = aa8aaaaa
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000000
TrainRcvEn56: RcvrEnDly 00000000
TrainRcvEn541: RcvrEnDly 00000001
QW0.lo : test_buf= fffb0bbc
value = 55555555
QW0.lo : addr_lo = 00500000
value = 55555555
QW0.hi : test_buf= fffb0bc0
value = 55555555
QW0.hi : addr_lo = 00500004
value = 55855555
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000001
TrainRcvEn56: RcvrEnDly 00000001
TrainRcvEn541: RcvrEnDly 00000002
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = aa8aaaaa
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000002
TrainRcvEn56: RcvrEnDly 00000002
TrainRcvEn541: RcvrEnDly 00000003
QW0.lo : test_buf= fffb0bbc
value = 55555555
QW0.lo : addr_lo = 00500000
value = 55555555
QW0.hi : test_buf= fffb0bc0
value = 55555555
QW0.hi : addr_lo = 00500004
value = 55555555
TrainRcvEn542: Test0 00000000
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = aaaaaaaa
TrainRcvEn543: Test1 00000000
TrainRcvEn55: RcvrEnDly 00000003
TrainRcvEn61: RcvrEnDly 00000003
TrainRcvEn63: RcvrEnDly 00000003
TrainRcvEn64: CTLRMaxDelay 00000003
TrainRcvEn52: index 00000013
TrainRcvEn52: index 00000016
TrainRcvEn52: index 00000019
TrainRcvEn51: channel 00000001
TrainRcvEn52: index 00000010
TrainRcvEn52: index 00000013
TrainRcvEn52: index 00000016
TrainRcvEn52: index 00000019
TrainRcvEn65: CTLRMaxDelay 00000003
CTLRMaxDelay=03
train_DqsRcvrEn: end ctrl 00000000
done
DQS Training:DQSPos: 00
train_DqsPos: begin ctrl 00000000
TrainDQSRdWrPos: 0 ctrl 00000000
TrainDQSRdWrPos: 1 channel 00000000
TrainDQSRdWrPos: 21 DQSWrDelay 00000000
TrainReadPos00000000
TrainDQSPos begin 00000000
TrainDQSPos: 11 ChipSel 00000000
TrainDQSPos: 12 TestAddr 00001000
TrainDQSPos: 13 for read so write at
first00000000
TrainDQSPos: 141 DQSDelay 00000000
TrainDQSPos: 142 MutualCSPassW 000000ff
TrainDQSPos: 144 Pattern 00000000
TrainDQSPos: 145 MutualCSPassW 000000ff
test_buf= 000cea20 value =
00000000
taddr_lo = 00100000 value =
ffffefff
bitmap = 000000f0
test_buf= 000cea24 value =
00000000
taddr_lo = 00100004 value =
dfffdfff
bitmap = 00000000
test_buf= 000cea28 value =
ffffffff
taddr_lo = 00100008 value =
ffffefff
bitmap = 00000000
test_buf= 000cea2c value =
ffffffff
taddr_lo = 0010000c value =
dfffdfff
bitmap = 00000000
test_buf= 000cea30 value =
00000000
taddr_lo = 00100010 value =
ffffffff
bitmap = 00000000
test_buf= 000cea34 value =
00000000
taddr_lo = 00100014 value =
ffffffff
bitmap = 00000000
test_buf= 000cea38 value =
00000000
taddr_lo = 00100018 value =
00000000
bitmap = 00000000
test_buf= 000cea3c value =
00000000
taddr_lo = 0010001c value =
00000000
bitmap = 00000000
test_buf= 000cea40 value =
00000000
taddr_lo = 00100020 value =
00000000
bitmap = 00000000
test_buf= 000cea44 value =
00000000
taddr_lo = 00100024 value =
00000000
bitmap = 00000000
test_buf= 000cea48 value =
ffffffff
taddr_lo = 00100028 value =
ffffefff
bitmap = 00000000
test_buf= 000cea4c value =
ffffffff
taddr_lo = 0010002c value =
dfffdfdf
bitmap = 00000000
test_buf= 000cea50 value =
00000000
taddr_lo = 00100030 value =
ffffffff
bitmap = 00000000
test_buf= 000cea54 value =
00000000
taddr_lo = 00100034 value =
ffffffff
bitmap = 00000000
test_buf= 000cea58 value =
00000000
coreboot-2.0.0.0Fallback Po èen 9 21:25:28 CEST 2008 starting...
now booting... fallback
coreboot-2.0.0.0Normal Po èen 9 21:25:06 CEST 2008 starting...
now booting... real_main
Enabling routing table for node 00 done.
Enabling UP settings
Disabling read/write/fill probes for UP... done.
coherent_ht_finalize
done
core0 started:
now booting... Core0 started
started ap apicid:
SBLink=00
NC node|link=00
0001K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05
VIA HT caps: 0075
HT between CPU and NB OK, not requesting reset
0101ht reset -
NO reset
after smbus
after memreset
Ram1.00
setting up CPU00 northbridge registers
done.
Ram2.00
Device error
Device error
Device error
Unbuffered
1 min_cycle_time:00000250
i:00000000
latencies:00000038
index:00000000
latency:00000003
value1:00000050
value2:00000500
new_cycle_time:00000500
new_latency:00000003
index:00000001
latency:00000004
value1:0000003d
value2:00000375
new_cycle_time:00000375
new_latency:00000004
index:00000002
latency:00000005
value1:0000003d
value2:00000375
new_cycle_time:00000375
new_latency:00000004
2 min_cycle_time:00000375
2 min_latency:00000004
3 min_cycle_time:00000375
3 min_latency:00000004
4 min_cycle_time:00000375
266Mhz
266Mhz
dimm socket: 00000000
trc
trcd
trrd
tras
update_dimm_Tras: 0 value=0000002d
update_dimm_Tras: 1 value=00000708
update_dimm_Tras: divisor=000000c8
update_dimm_Tras: clocks=00000009
trp
trtp
twr
tref
twtr
trfc
XRAM: 0x00080000 KB
Ram3
dimm_mask = 00000001
x4_mask = 00000000
x16_mask = 00000000
single_rank_mask = 00000001
ODC = 00111222
Addr Timing= 002f2f00
Initializing memory: done
sysinfo tom_k
00080000Setting variable MTRR 02, base: 0000MB, range: 0200MB, type WB
DQS Training:RcvrEn:Pass1: 00
train_DqsRcvrEn: begin ctrl 00000000
TrainRcvEn: 0 ctrl00000000
TrainRcvEn51: channel 00000000
TrainRcvEn52: index 00000010
TrainRcvEn53: TestAddr0B 00005000
TrainRcvEn541: RcvrEnDly 00000000
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaac1
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000000
TrainRcvEn56: RcvrEnDly 00000000
TrainRcvEn541: RcvrEnDly 00000001
QW0.lo : test_buf= fffb0bbc
value = 55555555
QW0.lo : addr_lo = 00500000
value = 55555551
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000001
TrainRcvEn56: RcvrEnDly 00000001
TrainRcvEn541: RcvrEnDly 00000002
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaa51
TrainRcvEn542: Test0 00000001
TrainRcvEn55: RcvrEnDly 00000002
TrainRcvEn56: RcvrEnDly 00000002
TrainRcvEn541: RcvrEnDly 00000003
QW0.lo : test_buf= fffb0bbc
value = 55555555
QW0.lo : addr_lo = 00500000
value = 55555555
QW0.hi : test_buf= fffb0bc0
value = 55555555
QW0.hi : addr_lo = 00500004
value = 55555555
TrainRcvEn542: Test0 00000000
QW0.lo : test_buf= fffb0bfc
value = aaaaaaaa
QW0.lo : addr_lo = 00100000
value = aaaaaaaa
QW0.hi : test_buf= fffb0c00
value = aaaaaaaa
QW0.hi : addr_lo = 00100004
value = aaaaaaaa
TrainRcvEn543: Test1 00000000
TrainRcvEn55: RcvrEnDly 00000003
TrainRcvEn61: RcvrEnDly 00000003
TrainRcvEn63: RcvrEnDly 00000003
TrainRcvEn64: CTLRMaxDelay 00000003
TrainRcvEn52: index 00000013
TrainRcvEn52: index 00000016
TrainRcvEn52: index 00000019
TrainRcvEn51: channel 00000001
TrainRcvEn52: index 00000010
TrainRcvEn52: index 00000013
TrainRcvEn52: index 00000016
TrainRcvEn52: index 00000019
TrainRcvEn65: CTLRMaxDelay 00000003
CTLRMaxDelay=03
train_DqsRcvrEn: end ctrl 00000000
done
DQS Training:DQSPos: 00
train_DqsPos: begin ctrl 00000000
TrainDQSRdWrPos: 0 ctrl 00000000
TrainDQSRdWrPos: 1 channel 00000000
TrainDQSRdWrPos: 21 DQSWrDelay 00000000
TrainReadPos00000000
TrainDQSPos begin 00000000
TrainDQSPos: 11 ChipSel 00000000
Tra
m.txt.sig
Description: Binary data
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