Author: stuge
Date: 2008-06-29 03:30:41 +0200 (Sun, 29 Jun 2008)
New Revision: 3395
Modified:
trunk/util/flashrom/chipset_enable.c
trunk/util/flashrom/ichspi.c
Log:
flashrom: Fix ICH7 non-SPI that broke in r3393
r3393 assumed that ICH7 always used SPI. This patch resets ich7_detected back
to 0 when BOOT BIOS Straps indicate something else than SPI.
Also fixes a build error in ichspi.c with gcc 4.2.2.
Signed-off-by: Peter Stuge <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: trunk/util/flashrom/chipset_enable.c
===================================================================
--- trunk/util/flashrom/chipset_enable.c 2008-06-28 23:02:22 UTC (rev
3394)
+++ trunk/util/flashrom/chipset_enable.c 2008-06-29 01:30:41 UTC (rev
3395)
@@ -212,6 +212,8 @@
bbs = (gcs >> 10) & 0x3;
printf_debug("BOOT BIOS Straps: 0x%x (%s)\n", bbs,
(bbs == 0x3) ? "LPC" : ((bbs == 0x2) ? "PCI" : "SPI"));
+ if (bbs >= 2)
+ ich7_detected = 0;
buc = *(volatile uint8_t *)(rcrb + 0x3414);
printf_debug("Top Swap : %s\n", (buc & 1)?"enabled (A16 inverted)":"not
enabled");
Modified: trunk/util/flashrom/ichspi.c
===================================================================
--- trunk/util/flashrom/ichspi.c 2008-06-28 23:02:22 UTC (rev 3394)
+++ trunk/util/flashrom/ichspi.c 2008-06-29 01:30:41 UTC (rev 3395)
@@ -229,7 +229,7 @@
{
int write_cmd = 0;
int timeout;
- uint32_t temp32;
+ uint32_t temp32 = 0;
uint16_t temp16;
uint32_t a;
--
coreboot mailing list
[email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
