On Sun, Jul 20, 2008 at 11:52 AM, Steve Casselman <[EMAIL PROTECTED]> wrote:
> Credits represent the number of buffers available. There are 7 types of > buffers in the Opteron used for the HT subsystem. Each HT link's transmitter > sends the receiver on the other side the number of credits (buffers) that > are available. If the chip is something like a south bridge then it has a > fixed number of credits (buffers) and it sends them to the Opteron. The > Opteron has a pool of buffers that can be shared among the three HT links it > has. > Steve, This was what I was looking for. Since the CK804 uses fewer than the default number of credits, I was wondering if a coprocessor could take the "extras" for the link it was on. Thanks, Myles > Their use is mostly in high speed data transfer where you want more data > buffers on one port than on another. > > As to the CK804 I'm thinking that Dr Lu double checked those settings in > the Nvidia data sheet. > > The total number of buffers allocated in your BIOS should be checked > against the information below. > > Steve > PS You can see these buffer numbers you have to be root.. > lspci -s 0:18.0 -xxx > > pcitweak -r 0:18:0 0x90 (reads LDT0 buffer counts) > > > From the BIOS and Kernel guide... > > 4.3.15 LDTi Buffer Count Registers > > > LDT0, LDT1, LDT2 Buffer Count Registers Function 0: Offset 90h, B0h, D0h > > Request Buffer Count (Req)—Bits 3–0. > Posted Request Buffer Count (PReq)—Bits 7–4. > Response Buffer Count (Rsp)—Bits 11–8. > Probe Buffer Count (Probe)—Bits 15–12. > Request Data Buffer Count (ReqD)—Bits 18–16. > Posted Request Data Buffer Count (PReqD)—Bits 22–20. > Response Data Buffer Count (RspD)—Bits 26–24. > > > > 4.6.10 XBAR Flow Control Buffers > > Table 28. XBAR Input Buffers > > Link Number of Number of > Command Buffers Data Buffers > > HT Link 0-2 16 x 3 8 x 3 > SRI 10 5 > MCT 12 8 > Total 70 37 > > XBAR command and data buffers are independent. There are 70 command buffers > available, but a maximum of 64 can be used at any given time. Number of used > data buffers is not restricted. The default allocation of command buffers > when all HyperTransport links are present is shown in Table 29. > > Default Command XBAR Buffers > > Link Number of > Command Buffers > > HT Link 0-2 15 x 3 > SRI 8 > MCT 11 > Total 64 > > > > > <http://www.coreboot.org/mailman/listinfo/coreboot> >
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