Hi,
r698 left me with the desire to put these new #defines to good use.
On 25.07.2008 21:44, [EMAIL PROTECTED] wrote:
> Author: rminnich
> New Revision: 698
>
> Add names for control bits.
> Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
> Acked-by: Marc Jones <[EMAIL PROTECTED]>
>
>
> Modified: coreboot-v3/include/arch/x86/amd_geodelx.h
> ===================================================================
> --- coreboot-v3/include/arch/x86/amd_geodelx.h 2008-07-20 21:05:25 UTC
> (rev 697)
> +++ coreboot-v3/include/arch/x86/amd_geodelx.h 2008-07-25 19:44:08 UTC
> (rev 698)
> @@ -230,6 +230,21 @@
> #define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8)
> #define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
>
> +/* Region CONFiguration registers (RCONF) */
> +/* There are control bits for memory configuration. They are at different
> + * offsets depending on the MSR. We define them here with values
> + * independent of their position in a 64-bit MSR, with a "shift" value
> + * to get them into the right place. To use them for, e.g., the
> + * CPU_RCONF_DEFAULT register, you would use
> + * RCONF_WT(RCONF_DEFAULT_LOWER_SYSRC_SHIFT)
> + */
> +#define RCONF_WS(x) (1<<(5+x)) /* Write-serialize */
> +#define RCONF_WC(x) (1<<(4+x)) /* Write-combine */
> +#define RCONF_WT(x) (1<<(3+x)) /* Write-through */
> +#define RCONF_WP(x) (1<<(2+x)) /* Write-protect */
> +#define RCONF_WA(x) (1<<(1+x)) /* Write-allocate */
> +#define RCONF_CD(x) (1<<(0+x)) /* Cache Disable */
> +
> #define CPU_RCONF_DEFAULT 0x1808
> #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
> #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
>
Hmm... that would mean we can change the GeodeLX CAR code a bit. RFC for
a patch follows.
I have no idea whether this is completely correct.
Index: arch/x86/geodelx/stage0.S
===================================================================
--- arch/x86/geodelx/stage0.S (Revision 698)
+++ arch/x86/geodelx/stage0.S (Arbeitskopie)
@@ -180,8 +180,10 @@
movl $CPU_RCONF_DEFAULT, %ecx
rdmsr
- /* 1MB system memory in write back 1|00100|00. */
- movl $0x010010000, %eax
+ /* 1 MB system memory (256 blocks of 4kB),
+ * disable cache between SYSTOP and ROMBASE.
+ */
+ movl
$(RCONF_CD(RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT)|(256<<RCONF_DEFAULT_LOWER_SYSTOP_SHIFT)),
%eax
wrmsr
/* In LX DCDIS is set after POR which disables the cache..., clear
Index: arch/x86/geodelx/stage1.c
===================================================================
--- arch/x86/geodelx/stage1.c (Revision 698)
+++ arch/x86/geodelx/stage1.c (Arbeitskopie)
@@ -26,7 +26,12 @@
static const struct msrinit msr_table[] = {
/* Setup access to cache under 1MB. */
- {CPU_RCONF_DEFAULT, {.hi = 0x24fffc02,.lo = 0x1000A000}}, // 0x00000-0xA0000
+ {CPU_RCONF_DEFAULT, {.hi = (RCONF_WS(RCONF_DEFAULT_UPPER_ROMRC_SHIFT)|
+ RCONF_WP(RCONF_DEFAULT_UPPER_ROMRC_SHIFT)|
+ (0xfffc<<RCONF_DEFAULT_UPPER_ROMBASE_SHIFT)|
+
RCONF_CD((RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT-32))),
+ .lo = RCONF_CD(RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT)|
+ (0x00A0<<RCONF_DEFAULT_LOWER_SYSTOP_SHIFT)}},
// 0x00000-0xA0000
{CPU_RCONF_A0_BF, {.hi = 0x00000000,.lo = 0x00000000}}, // 0xA0000-0xBFFFF
{CPU_RCONF_C0_DF, {.hi = 0x00000000,.lo = 0x00000000}}, // 0xC0000-0xDFFFF
{CPU_RCONF_E0_FF, {.hi = 0x00000000,.lo = 0x00000000}}, // 0xE0000-0xFFFFF
Regards,
Carl-Daniel
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http://www.hailfinger.org/
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