Author: rminnich
Date: 2008-07-30 17:08:25 +0200 (Wed, 30 Jul 2008)
New Revision: 700
Modified:
coreboot-v3/mainboard/adl/msm800sev/dts
coreboot-v3/mainboard/amd/db800/dts
coreboot-v3/mainboard/amd/norwich/dts
coreboot-v3/mainboard/artecgroup/dbe61/dts
coreboot-v3/mainboard/artecgroup/dbe62/dts
coreboot-v3/mainboard/pcengines/alix1c/dts
coreboot-v3/mainboard/pcengines/alix2c3/dts
coreboot-v3/util/dtc/flattree.c
Log:
1. fix dtc to properly put @x,y in hex, not decimal.
2. Fix trivial bug in dtc -- ioport is 6 chars long, not 3
3. Fix all dts so that the @ parts are now in hex.
4. fix graphics mem in dbs62 to be 16 MB, per artec.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/mainboard/adl/msm800sev/dts
===================================================================
--- coreboot-v3/mainboard/adl/msm800sev/dts 2008-07-29 15:54:46 UTC (rev
699)
+++ coreboot-v3/mainboard/adl/msm800sev/dts 2008-07-30 15:08:25 UTC (rev
700)
@@ -37,11 +37,11 @@
[EMAIL PROTECTED],1 {
/config/("southbridge/amd/cs5536/dts");
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
- [EMAIL PROTECTED] {
+ [EMAIL PROTECTED] {
/config/("superio/winbond/w83627hf/dts");
com1enable = "1";
};
Modified: coreboot-v3/mainboard/amd/db800/dts
===================================================================
--- coreboot-v3/mainboard/amd/db800/dts 2008-07-29 15:54:46 UTC (rev 699)
+++ coreboot-v3/mainboard/amd/db800/dts 2008-07-30 15:08:25 UTC (rev 700)
@@ -34,7 +34,7 @@
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/geodelx/pci");
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -48,11 +48,11 @@
enable_gpio_int_route = "0x0D0C0700";
enable_USBP4_device = "1";
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
- [EMAIL PROTECTED] {
+ [EMAIL PROTECTED] {
/config/("superio/winbond/w83627hf/dts");
com1enable = "1";
};
Modified: coreboot-v3/mainboard/amd/norwich/dts
===================================================================
--- coreboot-v3/mainboard/amd/norwich/dts 2008-07-29 15:54:46 UTC (rev
699)
+++ coreboot-v3/mainboard/amd/norwich/dts 2008-07-30 15:08:25 UTC (rev
700)
@@ -34,7 +34,7 @@
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/geodelx/pci");
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -51,7 +51,7 @@
com1_address = "0x3f8";
com1_irq = "4";
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
Modified: coreboot-v3/mainboard/artecgroup/dbe61/dts
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-07-29 15:54:46 UTC (rev
699)
+++ coreboot-v3/mainboard/artecgroup/dbe61/dts 2008-07-30 15:08:25 UTC (rev
700)
@@ -89,7 +89,7 @@
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/geodelx/pci");
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -110,7 +110,7 @@
com2_address = "0x3f8";
com2_irq = "4";
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
};
};
Modified: coreboot-v3/mainboard/artecgroup/dbe62/dts
===================================================================
--- coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-07-29 15:54:46 UTC (rev
699)
+++ coreboot-v3/mainboard/artecgroup/dbe62/dts 2008-07-30 15:08:25 UTC (rev
700)
@@ -28,11 +28,11 @@
[EMAIL PROTECTED] {
/config/("northbridge/amd/geodelx/domain");
/* Video RAM has to be in 2MB chunks. */
- geode_video_mb = "8";
+ geode_video_mb = "16";
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/geodelx/pci");
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -55,7 +55,7 @@
/* USB Port Power Handling setting. */
pph = "0xf5";
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
};
};
Modified: coreboot-v3/mainboard/pcengines/alix1c/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix1c/dts 2008-07-29 15:54:46 UTC (rev
699)
+++ coreboot-v3/mainboard/pcengines/alix1c/dts 2008-07-30 15:08:25 UTC (rev
700)
@@ -32,7 +32,7 @@
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/geodelx/pci");
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -45,11 +45,11 @@
* See virtual PIC spec. */
enable_gpio_int_route = "0x0D0C0700";
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
- [EMAIL PROTECTED] {
+ [EMAIL PROTECTED] {
/config/("superio/winbond/w83627hf/dts");
com1enable = "1";
};
Modified: coreboot-v3/mainboard/pcengines/alix2c3/dts
===================================================================
--- coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-07-29 15:54:46 UTC (rev
699)
+++ coreboot-v3/mainboard/pcengines/alix2c3/dts 2008-07-30 15:08:25 UTC (rev
700)
@@ -30,7 +30,7 @@
[EMAIL PROTECTED],0 {
/config/("northbridge/amd/geodelx/pci");
};
- [EMAIL PROTECTED],0 {
+ [EMAIL PROTECTED],0 {
/config/("southbridge/amd/cs5536/dts");
/* Interrupt enables for LPC bus.
* Each bit is an IRQ 0-15. */
@@ -49,7 +49,7 @@
/* this board does not really have vga; disable it (pci
device 00:01.1) */
unwanted_vpci = < 80000900 0 >;
};
- [EMAIL PROTECTED],2 {
+ [EMAIL PROTECTED],2 {
/config/("southbridge/amd/cs5536/ide");
enable_ide = "1";
};
Modified: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3/util/dtc/flattree.c 2008-07-29 15:54:46 UTC (rev 699)
+++ coreboot-v3/util/dtc/flattree.c 2008-07-30 15:08:25 UTC (rev 700)
@@ -551,27 +551,40 @@
if (path && path[1]) {
path++;
if (!strncmp(tree->name, "cpu", 3)){
- fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={
.id = %s }}},\n",
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={
.id = 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "bus", 3)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = %s }}},\n",
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "apic", 4)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_APIC,.u={.apic={ %s }}},\n",
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "domain", 6)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = %s }}},\n",
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "pci", 3)){
- fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={
.devfn = PCI_DEVFN(%s)}}},\n",
- path);
+ /* it's in two parts */
+ char *devfn = strdup(path);
+ char *dev = devfn;
+ char *fn;
+
+ fn = index(devfn, ',');
+ /* if there is no fn we assume 0 */
+ /* the Rules are unclear on this point */
+ if (fn)
+ *fn++ = 0;
+ else
+ fn = "0";
+
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={
.devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n",
+ dev, fn);
}
- if (!strncmp(tree->name, "ioport", 3)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=%s}}},\n",
+ if (!strncmp(tree->name, "ioport", 6)){
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n",
path);
}
}
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