see patch.
ron
Add side1, side2 to comon dimm_size struct.
The most controversial change here is that I am calling conf1 pci ops directly.
Downside: ugly.
Upside: it will work, it is known that conf1 applies to this board, it does not require
fakery in the style of v2, it does not require that we fake up partially-filled device structs
to make it "work" with pci_config_{read,write} and friends.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Index: include/arch/x86/amd/k8/k8.h
===================================================================
--- include/arch/x86/amd/k8/k8.h (revision 717)
+++ include/arch/x86/amd/k8/k8.h (working copy)
@@ -347,6 +347,7 @@
struct dimm_size {
u8 per_rank; // it is rows + col + bank_lines + data lines */
+ u8 side1, side2;
u8 rows;
u8 col;
u8 bank; //1, 2, 3 mean 2, 4, 8
@@ -371,10 +372,10 @@
} __attribute__((packed));
struct link_pair_st {
- struct device * udev;
+ u32 udev;
u32 upos;
u32 uoffs;
- struct device * dev;
+ u32 dev;
u32 pos;
u32 offs;
Index: include/arch/x86/amd/k8/raminit.h
===================================================================
--- include/arch/x86/amd/k8/raminit.h (revision 716)
+++ include/arch/x86/amd/k8/raminit.h (working copy)
@@ -8,7 +8,7 @@
#define DIMM_SOCKETS 4
struct mem_controller {
unsigned node_id;
- struct device *f0, *f1, *f2, *f3;
+ u32 f0, f1, f2, f3;
u16 channel0[DIMM_SOCKETS];
u16 channel1[DIMM_SOCKETS];
};
Index: include/arch/x86/macros.h
===================================================================
--- include/arch/x86/macros.h (revision 0)
+++ include/arch/x86/macros.h (revision 0)
@@ -0,0 +1,31 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2000 Ron G. Minnich <[EMAIL PROTECTED]>
+ * Copyright (C) 2007 Stefan Reinauer <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef ARCH_X86_MACROS_H
+#define ARCH_X86_MACROS_H
+
+#define port80_post(value) \
+ movb $value, %al; \
+ outb %al, $0x80
+
+
+
+#endif /* ARCH_X86_MACROS_H */
Index: northbridge/amd/k8/raminit.c
===================================================================
--- northbridge/amd/k8/raminit.c (revision 717)
+++ northbridge/amd/k8/raminit.c (working copy)
@@ -51,32 +51,33 @@
#define HW_MEM_HOLE_SIZEK 64*1024*1024
#endif
+
+/* now THIS is a kludge but ... it will do for now until we work this out. */
+extern const struct pci_bus_operations pci_cf8_conf1;
static void hard_reset(void);
static void setup_resource_map(const unsigned int *register_values, int max)
{
printk(BIOS_DEBUG, "setting up resource map....");
-/*
int i;
for(i = 0; i < max; i += 3) {
- struct device *dev;
+ u32 dev;
unsigned where;
unsigned long reg;
printk(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]);
dev = register_values[i] & ~0xfff;
where = register_values[i] & 0xfff;
- reg = pci_read_config32(dev, where);
+ reg = pci_cf8_conf1.read32(NULL, 0, dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
- pci_write_config32(dev, where, reg);
+ pci_cf8_conf1.write32(NULL, 0, dev, where, reg);
}
-*/
printk(BIOS_DEBUG, "done.\n");
}
static int controller_present(const struct mem_controller *ctrl)
{
- return pci_read_config32(ctrl->f0, 0) == 0x11001022;
+ return pci_cf8_conf1.read32(NULL, 0, ctrl->f0, 0) == 0x11001022;
}
static void sdram_set_registers(const struct mem_controller *ctrl)
@@ -559,16 +560,16 @@
printk(BIOS_SPEW, "setting up CPU 0x%x northbridge registers ", ctrl->node_id);
max = sizeof(register_values)/sizeof(register_values[0]);
for(i = 0; i < max; i += 3) {
- struct device *dev;
+ u32 dev;
unsigned where;
unsigned long reg;
printk(BIOS_DEBUG, "%08x <- %08x\n", register_values[i], register_values[i+2]);
dev = (register_values[i] & ~0xfff) - PCI_BDF(0, 0x18, 0) + ctrl->f0;
where = register_values[i] & 0xfff;
- reg = pci_read_config32(dev, where);
+ reg = pci_cf8_conf1.read32(NULL, 0, dev, where);
reg &= register_values[i+1];
reg |= register_values[i+2];
- pci_write_config32(dev, where, reg);
+ pci_cf8_conf1.write32(NULL, 0, dev, where, reg);
}
printk(BIOS_SPEW, "done.\n");
}
@@ -577,8 +578,8 @@
static void hw_enable_ecc(const struct mem_controller *ctrl)
{
u32 dcl, nbcap, opt = 1;
- nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ nbcap = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_DimmEccEn;
if (nbcap & NBCAP_ECC) {
dcl |= DCL_DimmEccEn;
@@ -586,14 +587,14 @@
if (get_option(&opt, "ECC_memory") || opt) {
dcl &= ~DCL_DimmEccEn;
}
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
static int is_dual_channel(const struct mem_controller *ctrl)
{
u32 dcl;
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
return dcl & DCL_128BitEn;
}
@@ -605,7 +606,7 @@
*/
#warning "FIXME: Implement a better test for Opterons"
u32 nbcap;
- nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+ nbcap = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);
return !!(nbcap & NBCAP_128Bit);
}
@@ -616,7 +617,7 @@
* This function must be called after spd_handle_unbuffered_dimms.
*/
u32 dcl;
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
return !(dcl & DCL_UnBufDimm);
}
@@ -748,25 +749,25 @@
base1 &= ~0x001ffffe;
/* Set the appropriate DIMM base address register */
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), base0);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), base1);
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (((index << 1)+4)<<2), base0);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (((index << 1)+5)<<2), base1);
}
#endif
/* Enable the memory clocks for this DIMM */
if (base0) {
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH);
dch |= DCH_MEMCLK_EN0 << index;
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
dch |= DCH_MEMCLK_EN0 << (index + 2);
}
#endif
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
}
@@ -782,7 +783,7 @@
u32 map;
u32 dch;
- map = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+ map = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_BANK_ADDR_MAP);
map &= ~(0xf << (index * 4));
#if QRANK_DIMM_SUPPORT == 1
if(sz.rank == 4) {
@@ -811,7 +812,7 @@
}
}
- pci_write_config32(ctrl->f2, DRAM_BANK_ADDR_MAP, map);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_BANK_ADDR_MAP, map);
}
@@ -843,7 +844,7 @@
unsigned base;
unsigned index;
unsigned limit_reg, base_reg;
- struct device *device;
+ u32 device;
node_id = ctrl->node_id;
index = (node_id << 3);
@@ -858,8 +859,8 @@
limit_reg = 0x44 + index;
base_reg = 0x40 + index;
for(device = PCI_BDF(0, 0x18, 1); device <= PCI_BDF(0, 0x1f, 1); device += PCI_BDF(0, 1, 0)) {
- pci_write_config32(device, limit_reg, limit);
- pci_write_config32(device, base_reg, base);
+ pci_cf8_conf1.write32(NULL, 0, device, limit_reg, limit);
+ pci_cf8_conf1.write32(NULL, 0, device, base_reg, base);
}
}
@@ -944,7 +945,7 @@
unsigned cs_mode;
u32 value;
- value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
@@ -960,7 +961,7 @@
return 0;
}
- value = pci_read_config32(ctrl->f2, DRAM_BANK_ADDR_MAP);
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_BANK_ADDR_MAP);
cs_mode =( value >> ((index>>1)*4)) & 0xf;
if(cs_mode == 0 ) continue;
if(common_cs_mode == 0) {
@@ -1013,13 +1014,13 @@
for(index = 0; index < 8; index++) {
u32 value;
- value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
continue;
}
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
- pci_write_config32(ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (index << 2), csbase);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSMASK + (index << 2), csmask);
csbase += csbase_inc;
}
@@ -1036,15 +1037,15 @@
/* Remember which registers we have used in the high 8 bits of tom */
tom = 0;
for(;;) {
- /* Find the largest remaining canidate */
- unsigned index, canidate;
+ /* Find the largest remaining candidate */
+ unsigned index, candidate;
u32 csbase, csmask;
unsigned size;
csbase = 0;
- canidate = 0;
+ candidate = 0;
for(index = 0; index < 8; index++) {
u32 value;
- value = pci_read_config32(ctrl->f2, DRAM_CSBASE + (index << 2));
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CSBASE + (index << 2));
/* Is it enabled? */
if (!(value & 1)) {
@@ -1060,11 +1061,11 @@
if (tom & (1 << (index + 24))) {
continue;
}
- /* I have a new canidate */
+ /* I have a new candidate */
csbase = value;
- canidate = index;
+ candidate = index;
}
- /* See if I have found a new canidate */
+ /* See if I have found a new candidate */
if (csbase == 0) {
break;
}
@@ -1073,7 +1074,7 @@
size = csbase >> 21;
/* Remember I have used this register */
- tom |= (1 << (canidate + 24));
+ tom |= (1 << (candidate + 24));
/* Recompute the cs base register value */
csbase = (tom << 21) | 1;
@@ -1086,9 +1087,9 @@
csmask |= 0xfe00; /* For now don't optimize */
/* Write the new base register */
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (canidate << 2), csbase);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (candidate << 2), csbase);
/* Write the new mask register */
- pci_write_config32(ctrl->f2, DRAM_CSMASK + (canidate << 2), csmask);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSMASK + (candidate << 2), csmask);
}
/* Return the memory size in K */
@@ -1105,10 +1106,10 @@
u32 limit, base;
unsigned index;
index = node_id << 3;
- base = pci_read_config32(ctrl->f1, 0x40 + index);
+ base = pci_cf8_conf1.read32(NULL, 0, ctrl->f1, 0x40 + index);
/* Only look at the limit if the base is enabled */
if ((base & 3) == 3) {
- limit = pci_read_config32(ctrl->f1, 0x44 + index);
+ limit = pci_cf8_conf1.read32(NULL, 0, ctrl->f1, 0x44 + index);
end_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
}
}
@@ -1139,8 +1140,8 @@
static long disable_dimm(const struct mem_controller *ctrl, unsigned index, long dimm_mask)
{
printk(BIOS_DEBUG, "disabling dimm 0x%x\n", index);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
- pci_write_config32(ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (((index << 1)+0)<<2), 0);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CSBASE + (((index << 1)+1)<<2), 0);
dimm_mask &= ~(1 << index);
return dimm_mask;
}
@@ -1176,7 +1177,7 @@
die("Mixed buffered and registered dimms not supported");
}
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_UnBufDimm;
if (unbuffered) {
if ((has_dualch) && (!is_cpu_pre_d0())) {
@@ -1192,7 +1193,7 @@
dcl |= DCL_UnBufDimm;
}
}
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
if (is_registered(ctrl)) {
printk(BIOS_DEBUG, "Registered\n");
} else {
@@ -1260,7 +1261,7 @@
goto single_channel;
}
/* If the cpu is not capable of doing dual channels don't do dual channels */
- nbcap = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+ nbcap = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);
if (!(nbcap & NBCAP_128Bit)) {
goto single_channel;
}
@@ -1292,10 +1293,10 @@
}
printk(BIOS_SPEW, "Enabling dual channel memory\n");
u32 dcl;
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_32ByteEn;
dcl |= DCL_128BitEn;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
return dimm_mask;
single_channel:
dimm_mask &= ~((1 << (DIMM_SOCKETS *2)) - (1 << DIMM_SOCKETS));
@@ -1416,7 +1417,7 @@
[NBCAP_MEMCLK_100MHZ] = 0xa0, /* 10ns */
};
- value = pci_read_config32(ctrl->f3, NORTHBRIDGE_CAP);
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value >> NBCAP_MEMCLK_SHIFT) & NBCAP_MEMCLK_MASK];
@@ -1567,7 +1568,7 @@
result.param = get_mem_param(min_cycle_time);
/* Update DRAM Config High with our selected memory speed */
- value = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH);
value &= ~(DCH_MEMCLK_MASK << DCH_MEMCLK_SHIFT);
#if 0
/* Improves DQS centering by correcting for case when core speed multiplier and MEMCLK speed
@@ -1581,14 +1582,14 @@
#endif
value |= result.param->dch_memclk;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, value);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH, value);
static const unsigned latencies[] = { DTL_CL_2, DTL_CL_2_5, DTL_CL_3 };
/* Update DRAM Timing Low with our selected cas latency */
- value = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ value = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
value &= ~(DTL_TCL_MASK << DTL_TCL_SHIFT);
value |= latencies[min_latency - 2] << DTL_TCL_SHIFT;
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, value);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, value);
result.dimm_mask = dimm_mask;
return result;
@@ -1617,14 +1618,14 @@
return 0;
}
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRC_SHIFT) & DTL_TRC_MASK) + DTL_TRC_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRC_MASK << DTL_TRC_SHIFT);
dtl |= ((clocks - DTL_TRC_BASE) << DTL_TRC_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1645,14 +1646,14 @@
if (clocks > DTL_TRFC_MAX) {
return 0;
}
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRFC_SHIFT) & DTL_TRFC_MASK) + DTL_TRFC_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRFC_MASK << DTL_TRFC_SHIFT);
dtl |= ((clocks - DTL_TRFC_BASE) << DTL_TRFC_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1671,14 +1672,14 @@
if (clocks > DTL_TRCD_MAX) {
return 0;
}
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRCD_SHIFT) & DTL_TRCD_MASK) + DTL_TRCD_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRCD_MASK << DTL_TRCD_SHIFT);
dtl |= ((clocks - DTL_TRCD_BASE) << DTL_TRCD_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1696,14 +1697,14 @@
if (clocks > DTL_TRRD_MAX) {
return 0;
}
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRRD_SHIFT) & DTL_TRRD_MASK) + DTL_TRRD_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRRD_MASK << DTL_TRRD_SHIFT);
dtl |= ((clocks - DTL_TRRD_BASE) << DTL_TRRD_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1721,14 +1722,14 @@
if (clocks > DTL_TRAS_MAX) {
return 0;
}
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRAS_SHIFT) & DTL_TRAS_MASK) + DTL_TRAS_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRAS_MASK << DTL_TRAS_SHIFT);
dtl |= ((clocks - DTL_TRAS_BASE) << DTL_TRAS_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
@@ -1746,34 +1747,34 @@
if (clocks > DTL_TRP_MAX) {
return 0;
}
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
old_clocks = ((dtl >> DTL_TRP_SHIFT) & DTL_TRP_MASK) + DTL_TRP_BASE;
if (old_clocks > clocks) {
clocks = old_clocks;
}
dtl &= ~(DTL_TRP_MASK << DTL_TRP_SHIFT);
dtl |= ((clocks - DTL_TRP_BASE) << DTL_TRP_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
return 1;
}
static void set_Twr(const struct mem_controller *ctrl, const struct mem_param *param)
{
u32 dtl;
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
dtl &= ~(DTL_TWR_MASK << DTL_TWR_SHIFT);
dtl |= (param->dtl_twr - DTL_TWR_BASE) << DTL_TWR_SHIFT;
- pci_write_config32(ctrl->f2, DRAM_TIMING_LOW, dtl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW, dtl);
}
static void init_Tref(const struct mem_controller *ctrl, const struct mem_param *param)
{
u32 dth;
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
dth |= (param->dch_tref4k << DTH_TREF_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static int update_dimm_Tref(const struct mem_controller *ctrl, const struct mem_param *param, int i)
@@ -1790,7 +1791,7 @@
tref = param->dch_tref4k;
}
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH);
old_tref = (dth >> DTH_TREF_SHIFT) & DTH_TREF_MASK;
if ((value == 12) && (old_tref == param->dch_tref4k)) {
tref = param->dch_tref4k;
@@ -1799,7 +1800,7 @@
}
dth &= ~(DTH_TREF_MASK << DTH_TREF_SHIFT);
dth |= (tref << DTH_TREF_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH, dth);
return 1;
}
@@ -1830,12 +1831,12 @@
dimm |= 1<<(DCL_x4DIMM_SHIFT+i+2);
}
#endif
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~dimm;
if (value == 4) {
dcl |= dimm;
}
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
return 1;
}
@@ -1848,9 +1849,9 @@
return -1;
}
if (value != 2) {
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW);
dcl &= ~DCL_DimmEccEn;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
return 1;
}
@@ -1862,7 +1863,7 @@
dimms = 0;
for(index = 0; index < 8; index += 2) {
u32 csbase;
- csbase = pci_read_config32(ctrl->f2, (DRAM_CSBASE + (index << 2)));
+ csbase = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, (DRAM_CSBASE + (index << 2)));
if (csbase & 1) {
dimms += 1;
}
@@ -1874,10 +1875,10 @@
{
u32 dth;
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TWTR_MASK << DTH_TWTR_SHIFT);
dth |= ((param->dtl_twtr - DTH_TWTR_BASE) << DTH_TWTR_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH, dth);
}
static void set_Trwt(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1888,7 +1889,7 @@
int lat, mtype;
clocks = 0;
- dtl = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW);
+ dtl = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_LOW);
latency = (dtl >> DTL_TCL_SHIFT) & DTL_TCL_MASK;
if (is_opteron(ctrl)) {
@@ -1918,10 +1919,10 @@
die("Unknown Trwt\n");
}
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TRWT_MASK << DTH_TRWT_SHIFT);
dth |= ((clocks - DTH_TRWT_BASE) << DTH_TRWT_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH, dth);
return;
}
@@ -1935,10 +1936,10 @@
} else {
clocks = 1;
}
- dth = pci_read_config32(ctrl->f2, DRAM_TIMING_HIGH);
+ dth = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH);
dth &= ~(DTH_TWCL_MASK << DTH_TWCL_SHIFT);
dth |= ((clocks - DTH_TWCL_BASE) << DTH_TWCL_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_TIMING_HIGH, dth);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_TIMING_HIGH, dth);
}
@@ -1969,7 +1970,7 @@
die("Unknown rdpreamble for this nr of slots");
}
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH);
dch &= ~(DCH_RDPREAMBLE_MASK << DCH_RDPREAMBLE_SHIFT);
rdpreamble = param->rdpreamble[i];
@@ -1978,7 +1979,7 @@
}
dch |= (rdpreamble - DCH_RDPREAMBLE_BASE) << DCH_RDPREAMBLE_SHIFT;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_max_async_latency(const struct mem_controller *ctrl, const struct mem_param *param)
@@ -1989,7 +1990,7 @@
dimms = count_dimms(ctrl);
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH);
dch &= ~(DCH_ASYNC_LAT_MASK << DCH_ASYNC_LAT_SHIFT);
async_lat = 0;
if (is_registered(ctrl)) {
@@ -2016,18 +2017,18 @@
}
}
dch |= ((async_lat - DCH_ASYNC_LAT_BASE) << DCH_ASYNC_LAT_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static void set_idle_cycle_limit(const struct mem_controller *ctrl, const struct mem_param *param)
{
u32 dch;
/* AMD says to Hardcode this */
- dch = pci_read_config32(ctrl->f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH);
dch &= ~(DCH_IDLE_LIMIT_MASK << DCH_IDLE_LIMIT_SHIFT);
dch |= DCH_IDLE_LIMIT_16 << DCH_IDLE_LIMIT_SHIFT;
dch |= DCH_DYN_IDLE_CTR_EN;
- pci_write_config32(ctrl->f2, DRAM_CONFIG_HIGH, dch);
+ pci_cf8_conf1.write32(NULL, 0, ctrl->f2, DRAM_CONFIG_HIGH, dch);
}
static long spd_set_dram_timing(const struct mem_controller *ctrl, const struct mem_param *param, long dimm_mask)
@@ -2124,7 +2125,7 @@
{
int ii;
u32 carry_over;
- struct device *dev;
+ u32 dev;
u32 base, limit;
u32 basek;
u32 hoist;
@@ -2133,22 +2134,22 @@
carry_over = (4*1024*1024) - hole_startk;
for(ii=controllers - 1;ii>i;ii--) {
- base = pci_read_config32(ctrl[0].f1, 0x40 + (ii << 3));
+ base = pci_cf8_conf1.read32(NULL, 0, ctrl[0].f1, 0x40 + (ii << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- limit = pci_read_config32(ctrl[0].f1, 0x44 + (ii << 3));
+ limit = pci_cf8_conf1.read32(NULL, 0, ctrl[0].f1, 0x44 + (ii << 3));
for(j = 0; j < controllers; j++) {
- pci_write_config32(ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
- pci_write_config32(ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
+ pci_cf8_conf1.write32(NULL, 0, ctrl[j].f1, 0x44 + (ii << 3), limit + (carry_over << 2));
+ pci_cf8_conf1.write32(NULL, 0, ctrl[j].f1, 0x40 + (ii << 3), base + (carry_over << 2));
}
}
- limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+ limit = pci_cf8_conf1.read32(NULL, 0, ctrl[0].f1, 0x44 + (i << 3));
for(j = 0; j < controllers; j++) {
- pci_write_config32(ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
+ pci_cf8_conf1.write32(NULL, 0, ctrl[j].f1, 0x44 + (i << 3), limit + (carry_over << 2));
}
dev = ctrl[i].f1;
- base = pci_read_config32(dev, 0x40 + (i << 3));
+ base = pci_cf8_conf1.read32(NULL, 0, dev, 0x40 + (i << 3));
basek = (base & 0xffff0000) >> 2;
if(basek == hole_startk) {
//don't need set memhole here, because hole off set will be 0, overflow
@@ -2156,7 +2157,7 @@
base &= 0x0000ffff;
base |= (4*1024*1024)<<2;
for(j = 0; j < controllers; j++) {
- pci_write_config32(ctrl[j].f1, 0x40 + (i<<3), base);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[j].f1, 0x40 + (i<<3), base);
}
}
else {
@@ -2166,7 +2167,7 @@
(((basek + carry_over) >> 6) & 0x0000ff00) +
/* enable */
1;
- pci_write_config32(dev, 0xf0, hoist);
+ pci_cf8_conf1.write32(NULL, 0, dev, 0xf0, hoist);
}
return carry_over;
@@ -2179,7 +2180,8 @@
int i;
hole_startk = 4*1024*1024 - HW_MEM_HOLE_SIZEK;
-
+#warning "fix HW_MEM_HOLE_SIZE_AUTO_INC 1"
+#define HW_MEM_HOLE_SIZE_AUTO_INC 1
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
/* We need to double check if hole_startk is valid.
* If it is equal to the dram base address in K (base_k),
@@ -2189,7 +2191,7 @@
for(i=0; i<controllers; i++) {
u32 base;
unsigned base_k;
- base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+ base = pci_cf8_conf1.read32(NULL, 0, ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
@@ -2209,11 +2211,11 @@
for(i=0; i<controllers; i++) {
u32 base, limit;
unsigned base_k, limit_k;
- base = pci_read_config32(ctrl[0].f1, 0x40 + (i << 3));
+ base = pci_cf8_conf1.read32(NULL, 0, ctrl[0].f1, 0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
- limit = pci_read_config32(ctrl[0].f1, 0x44 + (i << 3));
+ limit = pci_cf8_conf1.read32(NULL, 0, ctrl[0].f1, 0x44 + (i << 3));
base_k = (base & 0xffff0000) >> 2;
limit_k = ((limit + 0x00010000) & 0xffff0000) >> 2;
if ((base_k <= hole_startk) && (limit_k > hole_startk)) {
@@ -2244,17 +2246,17 @@
u32 dch;
if (!controller_present(ctrl + i))
continue;
- dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_HIGH);
if (dch & (DCH_MEMCLK_EN0|DCH_MEMCLK_EN1|DCH_MEMCLK_EN2|DCH_MEMCLK_EN3)) {
dch |= DCH_MEMCLK_VALID;
- pci_write_config32(ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_HIGH, dch);
}
else {
/* Disable dram receivers */
u32 dcl;
- dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW);
dcl |= DCL_DisInRcvrs;
- pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
}
@@ -2268,31 +2270,31 @@
if (!controller_present(ctrl + i))
continue;
/* Skip everything if I don't have any memory on this controller */
- dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_HIGH);
if (!(dch & DCH_MEMCLK_VALID)) {
continue;
}
/* Toggle DisDqsHys to get it working */
- dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW);
if (dcl & DCL_DimmEccEn) {
u32 mnc;
printk(BIOS_SPEW, "ECC enabled\n");
- mnc = pci_read_config32(ctrl[i].f3, MCA_NB_CONFIG);
+ mnc = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f3, MCA_NB_CONFIG);
mnc |= MNC_ECC_EN;
if (dcl & DCL_128BitEn) {
mnc |= MNC_CHIPKILL_EN;
}
- pci_write_config32(ctrl[i].f3, MCA_NB_CONFIG, mnc);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[i].f3, MCA_NB_CONFIG, mnc);
}
dcl |= DCL_DisDqsHys;
- pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
dcl &= ~DCL_DisDqsHys;
dcl &= ~DCL_DLL_Disable;
dcl &= ~DCL_D_DRV;
dcl &= ~DCL_QFC_EN;
dcl |= DCL_DramInit;
- pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
}
for(i = 0; i < controllers; i++) {
@@ -2300,7 +2302,7 @@
if (!controller_present(ctrl + i))
continue;
/* Skip everything if I don't have any memory on this controller */
- dch = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_HIGH);
+ dch = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_HIGH);
if (!(dch & DCH_MEMCLK_VALID)) {
continue;
}
@@ -2309,7 +2311,7 @@
int loops = 0;
do {
- dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW);
loops += 1;
if ((loops & 1023) == 0) {
printk(BIOS_DEBUG, ".");
@@ -2323,9 +2325,9 @@
if (!is_cpu_pre_c0()) {
/* Wait until it is safe to touch memory */
dcl &= ~(DCL_MemClrStatus | DCL_DramEnable);
- pci_write_config32(ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
+ pci_cf8_conf1.write32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW, dcl);
do {
- dcl = pci_read_config32(ctrl[i].f2, DRAM_CONFIG_LOW);
+ dcl = pci_cf8_conf1.read32(NULL, 0, ctrl[i].f2, DRAM_CONFIG_LOW);
} while(((dcl & DCL_MemClrStatus) == 0) || ((dcl & DCL_DramEnable) == 0) );
}
--
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