Author: hailfinger
Date: 2008-08-10 02:20:24 +0200 (Sun, 10 Aug 2008)
New Revision: 730
Modified:
coreboot-v3/arch/x86/geodelx/cpu.c
coreboot-v3/device/agp_device.c
coreboot-v3/device/device_util.c
coreboot-v3/device/hypertransport.c
coreboot-v3/device/pci_device.c
coreboot-v3/device/pci_ops.c
coreboot-v3/device/pci_rom.c
coreboot-v3/device/pcie_device.c
coreboot-v3/device/pcix_device.c
coreboot-v3/device/pnp_device.c
coreboot-v3/include/device/device.h
coreboot-v3/include/device/path.h
coreboot-v3/mainboard/emulation/qemu-x86/vga.c
coreboot-v3/northbridge/amd/geodelx/geodelx.c
coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
coreboot-v3/southbridge/amd/cs5536/cs5536.c
coreboot-v3/southbridge/intel/i82371eb/i82371eb.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
coreboot-v3/superio/fintek/f71805f/superio.c
coreboot-v3/superio/ite/it8716f/superio.c
coreboot-v3/superio/winbond/w83627hf/superio.c
coreboot-v3/util/dtc/flattree.c
coreboot-v3/util/x86emu/biosemu.c
coreboot-v3/util/x86emu/pcbios/pcibios.c
coreboot-v3/util/x86emu/vm86.c
Log:
The named unions in the device tree code are obnoxious and degrade
readability. Move to anonymous unions.
Build tested on all targets. Boot tested on qemu.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Ron tested this and it boots to Linux.
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/geodelx/cpu.c
===================================================================
--- coreboot-v3/arch/x86/geodelx/cpu.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/arch/x86/geodelx/cpu.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -94,7 +94,7 @@
struct device_operations geodelx_cpuops = {
{.id = {.type = DEVICE_ID_PCI,
/* TODO: This is incorrect, these are _not_ PCI IDs! */
- .u = {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
+ {.pci = {.vendor = X86_VENDOR_AMD,.device = 0x05A2}}},
.ops = &geodelx_cpuops} .constructor =
default_device_constructor,
.phase3_scan = NULL,
.phase6_init = lx_init,
Modified: coreboot-v3/device/agp_device.c
===================================================================
--- coreboot-v3/device/agp_device.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/agp_device.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -40,8 +40,8 @@
struct device *child;
max = pci_scan_bus(bus, min_devfn, max_devfn, max);
for (child = bus->children; child; child = child->sibling) {
- if ((child->path.u.pci.devfn < min_devfn) ||
- (child->path.u.pci.devfn > max_devfn)) {
+ if ((child->path.pci.devfn < min_devfn) ||
+ (child->path.pci.devfn > max_devfn)) {
continue;
}
agp_tune_dev(child);
Modified: coreboot-v3/device/device_util.c
===================================================================
--- coreboot-v3/device/device_util.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/device_util.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -81,7 +81,7 @@
for (dev = all_devices; dev; dev = dev->next) {
if ((dev->path.type == DEVICE_PATH_PCI) &&
(dev->bus->secondary == bus) &&
- (dev->path.u.pci.devfn == devfn)) {
+ (dev->path.pci.devfn == devfn)) {
result = dev;
break;
}
@@ -104,7 +104,7 @@
for (dev = all_devices; dev; dev = dev->next) {
if ((dev->path.type == DEVICE_PATH_I2C) &&
(dev->bus->secondary == bus) &&
- (dev->path.u.i2c.device == addr)) {
+ (dev->path.i2c.device == addr)) {
result = dev;
break;
}
@@ -155,8 +155,8 @@
struct device_id id;
id.type = DEVICE_ID_PCI;
- id.u.pci.vendor = vendor;
- id.u.pci.device = device;
+ id.pci.vendor = vendor;
+ id.pci.device = device;
return dev_find_device(&id, from);
}
@@ -197,48 +197,48 @@
sprintf(buffer, "PCI: %04x:%02x:%02x.%01x",
dev->bus->secondary >> 8,
dev->bus->secondary & 0xff,
- PCI_SLOT(dev->path.u.pci.devfn),
- PCI_FUNC(dev->path.u.pci.devfn));
+ PCI_SLOT(dev->path.pci.devfn),
+ PCI_FUNC(dev->path.pci.devfn));
#else
sprintf(buffer, "PCI: %02x:%02x.%01x",
dev->bus->secondary,
- PCI_SLOT(dev->path.u.pci.devfn),
- PCI_FUNC(dev->path.u.pci.devfn));
+ PCI_SLOT(dev->path.pci.devfn),
+ PCI_FUNC(dev->path.pci.devfn));
#endif
break;
case DEVICE_PATH_PNP:
sprintf(buffer, "PNP: %04x.%01x",
- dev->path.u.pnp.port, dev->path.u.pnp.device);
+ dev->path.pnp.port, dev->path.pnp.device);
break;
case DEVICE_PATH_I2C:
sprintf(buffer, "I2C: %02x:%02x",
- dev->bus->secondary, dev->path.u.i2c.device);
+ dev->bus->secondary, dev->path.i2c.device);
break;
case DEVICE_PATH_APIC:
- sprintf(buffer, "APIC: %02x", dev->path.u.apic.apic_id);
+ sprintf(buffer, "APIC: %02x", dev->path.apic.apic_id);
break;
case DEVICE_PATH_PCI_DOMAIN:
sprintf(buffer, "PCI_DOMAIN: %04x",
- dev->path.u.pci_domain.domain);
+ dev->path.pci_domain.domain);
break;
case DEVICE_PATH_PCI_BUS:
sprintf(buffer, "PCI_BUS: %04x",
- dev->path.u.pci_bus.bus);
+ dev->path.pci_bus.bus);
break;
case DEVICE_PATH_APIC_CLUSTER:
sprintf(buffer, "APIC_CLUSTER: %01x",
- dev->path.u.apic_cluster.cluster);
+ dev->path.apic_cluster.cluster);
break;
case DEVICE_PATH_CPU:
- sprintf(buffer, "CPU: %02x", dev->path.u.cpu.id);
+ sprintf(buffer, "CPU: %02x", dev->path.cpu.id);
break;
case DEVICE_PATH_CPU_BUS:
sprintf(buffer, "CPU_BUS: %02x",
- dev->path.u.cpu_bus.id);
+ dev->path.cpu_bus.id);
break;
case DEVICE_PATH_IOPORT:
sprintf(buffer, "IOPORT: %02x",
- dev->path.u.ioport.iobase);
+ dev->path.ioport.iobase);
break;
default:
printk(BIOS_ERR, "%s: Unknown device path type: %d\n",
@@ -262,36 +262,36 @@
memcpy(buffer, "Root Device", 12);
break;
case DEVICE_ID_PCI:
- sprintf(buffer, "PCI: %04x:%04x", id->u.pci.vendor,
- id->u.pci.device);
+ sprintf(buffer, "PCI: %04x:%04x", id->pci.vendor,
+ id->pci.device);
break;
case DEVICE_ID_PNP:
- sprintf(buffer, "PNP: %04x", id->u.pnp.device);
+ sprintf(buffer, "PNP: %04x", id->pnp.device);
break;
case DEVICE_ID_I2C:
- sprintf(buffer, "I2C: %04x", id->u.i2c.id);
+ sprintf(buffer, "I2C: %04x", id->i2c.id);
break;
case DEVICE_ID_APIC:
- sprintf(buffer, "APIC: %02x:%02x", id->u.apic.vendor,
- id->u.apic.device);
+ sprintf(buffer, "APIC: %02x:%02x", id->apic.vendor,
+ id->apic.device);
break;
case DEVICE_ID_PCI_DOMAIN:
sprintf(buffer, "PCI_DOMAIN: %04x:%04x",
- id->u.pci_domain.vendor,
- id->u.pci_domain.device);
+ id->pci_domain.vendor,
+ id->pci_domain.device);
break;
case DEVICE_ID_APIC_CLUSTER:
sprintf(buffer, "APIC_CLUSTER: %02x:%02x",
- id->u.apic_cluster.vendor,
- id->u.apic_cluster.device);
+ id->apic_cluster.vendor,
+ id->apic_cluster.device);
break;
case DEVICE_ID_CPU:
- sprintf(buffer, "CPU", id->u.cpu.cpuid[0],
- id->u.cpu.cpuid[1], id->u.cpu.cpuid[2]);
+ sprintf(buffer, "CPU", id->cpu.cpuid[0],
+ id->cpu.cpuid[1], id->cpu.cpuid[2]);
break;
case DEVICE_ID_CPU_BUS:
sprintf(buffer, "CPU_BUS: %02x:%02x",
- id->u.cpu_bus.vendor, id->u.cpu_bus.device);
+ id->cpu_bus.vendor, id->cpu_bus.device);
break;
default:
printk(BIOS_ERR, "%s: Unknown device ID type: %d\n",
@@ -321,34 +321,34 @@
equal = 1;
break;
case DEVICE_PATH_PCI:
- equal = (path1->u.pci.devfn == path2->u.pci.devfn);
+ equal = (path1->pci.devfn == path2->pci.devfn);
break;
case DEVICE_PATH_PNP:
- equal = (path1->u.pnp.port == path2->u.pnp.port) &&
- (path1->u.pnp.device == path2->u.pnp.device);
+ equal = (path1->pnp.port == path2->pnp.port) &&
+ (path1->pnp.device == path2->pnp.device);
break;
case DEVICE_PATH_I2C:
- equal = (path1->u.i2c.device == path2->u.i2c.device);
+ equal = (path1->i2c.device == path2->i2c.device);
break;
case DEVICE_PATH_APIC:
equal =
- (path1->u.apic.apic_id == path2->u.apic.apic_id);
+ (path1->apic.apic_id == path2->apic.apic_id);
break;
case DEVICE_PATH_PCI_DOMAIN:
equal =
- (path1->u.pci_domain.domain ==
- path2->u.pci_domain.domain);
+ (path1->pci_domain.domain ==
+ path2->pci_domain.domain);
break;
case DEVICE_PATH_APIC_CLUSTER:
equal =
- (path1->u.apic_cluster.cluster ==
- path2->u.apic_cluster.cluster);
+ (path1->apic_cluster.cluster ==
+ path2->apic_cluster.cluster);
break;
case DEVICE_PATH_CPU:
- equal = (path1->u.cpu.id == path2->u.cpu.id);
+ equal = (path1->cpu.id == path2->cpu.id);
break;
case DEVICE_PATH_CPU_BUS:
- equal = (path1->u.cpu_bus.id == path2->u.cpu_bus.id);
+ equal = (path1->cpu_bus.id == path2->cpu_bus.id);
break;
default:
printk(BIOS_ERR, "Unknown device type: %d\n",
@@ -370,41 +370,41 @@
equal = 1;
break;
case DEVICE_ID_PCI:
- equal = (path1->u.pci.vendor == path2->u.pci.vendor)
- && (path1->u.pci.device == path2->u.pci.device);
+ equal = (path1->pci.vendor == path2->pci.vendor)
+ && (path1->pci.device == path2->pci.device);
break;
case DEVICE_ID_PNP:
- equal = (path1->u.pnp.device == path2->u.pnp.device);
+ equal = (path1->pnp.device == path2->pnp.device);
break;
case DEVICE_ID_I2C:
- equal = (path1->u.i2c.id == path2->u.i2c.id);
+ equal = (path1->i2c.id == path2->i2c.id);
break;
case DEVICE_ID_APIC:
- equal = (path1->u.apic.vendor == path2->u.apic.vendor)
- && (path1->u.apic.device == path2->u.apic.device);
+ equal = (path1->apic.vendor == path2->apic.vendor)
+ && (path1->apic.device == path2->apic.device);
break;
case DEVICE_ID_PCI_DOMAIN:
equal =
- (path1->u.pci_domain.vendor ==
- path2->u.pci_domain.vendor)
- && (path1->u.pci_domain.device ==
- path2->u.pci_domain.device);
+ (path1->pci_domain.vendor ==
+ path2->pci_domain.vendor)
+ && (path1->pci_domain.device ==
+ path2->pci_domain.device);
break;
case DEVICE_ID_APIC_CLUSTER:
equal =
- (path1->u.apic_cluster.vendor ==
- path2->u.apic_cluster.vendor)
- && (path1->u.apic_cluster.device ==
- path2->u.apic_cluster.device);
+ (path1->apic_cluster.vendor ==
+ path2->apic_cluster.vendor)
+ && (path1->apic_cluster.device ==
+ path2->apic_cluster.device);
break;
case DEVICE_ID_CPU:
- equal = (path1->u.cpu.cpuid == path2->u.cpu.cpuid);
+ equal = (path1->cpu.cpuid == path2->cpu.cpuid);
break;
case DEVICE_ID_CPU_BUS:
equal =
- (path1->u.cpu_bus.vendor == path2->u.cpu_bus.vendor)
- && (path1->u.cpu_bus.device ==
- path2->u.cpu_bus.device);
+ (path1->cpu_bus.vendor == path2->cpu_bus.vendor)
+ && (path1->cpu_bus.device ==
+ path2->cpu_bus.device);
break;
default:
printk(BIOS_ERR, "Unknown device type: %d\n",
Modified: coreboot-v3/device/hypertransport.c
===================================================================
--- coreboot-v3/device/hypertransport.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/hypertransport.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -50,7 +50,7 @@
*/
while (last && last->sibling &&
(last->sibling->path.type == DEVICE_PATH_PCI) &&
- (last->sibling->path.u.pci.devfn > last->path.u.pci.devfn)) {
+ (last->sibling->path.pci.devfn > last->path.pci.devfn)) {
last = last->sibling;
}
if (first) {
@@ -344,7 +344,7 @@
u32 id;
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.u.pci.devfn = PCI_DEVFN(0, 0);
+ dummy.path.pci.devfn = PCI_DEVFN(0, 0);
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
if (!((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000))) {
@@ -361,7 +361,7 @@
unsigned int pos, flags;
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.u.pci.devfn = devfn;
+ dummy.path.pci.devfn = devfn;
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
if ((id == 0xffffffff) || (id == 0x00000000) ||
(id == 0x0000ffff) || (id == 0xffff0000)) {
@@ -498,9 +498,9 @@
/* Update the unitid in the device structure. */
static_count = 1;
for (func = dev; func; func = func->sibling) {
- func->path.u.pci.devfn += (next_unitid << 3);
- static_count = (func->path.u.pci.devfn >> 3)
- - (dev->path.u.pci.devfn >> 3) + 1;
+ func->path.pci.devfn += (next_unitid << 3);
+ static_count = (func->path.pci.devfn >> 3)
+ - (dev->path.pci.devfn >> 3) + 1;
last_func = func;
}
@@ -557,7 +557,7 @@
flags);
for (func = real_last_dev; func; func = func->sibling) {
- func->path.u.pci.devfn -=
+ func->path.pci.devfn -=
((real_last_unitid -
HT_CHAIN_END_UNITID_BASE) << 3);
last_func = func;
Modified: coreboot-v3/device/pci_device.c
===================================================================
--- coreboot-v3/device/pci_device.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/pci_device.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -894,8 +894,8 @@
continue;
}
printk(BIOS_SPEW, "%s: check dev %s it has devfn 0x%02x\n",
- __func__, (*list)->dtsname, (*list)->path.u.pci.devfn);
- if ((*list)->path.u.pci.devfn == devfn) {
+ __func__, (*list)->dtsname, (*list)->path.pci.devfn);
+ if ((*list)->path.pci.devfn == devfn) {
/* Unlink from the list. */
dev = *list;
*list = (*list)->sibling;
@@ -948,7 +948,7 @@
struct device_id devid;
dummy.bus = bus;
dummy.path.type = DEVICE_PATH_PCI;
- dummy.path.u.pci.devfn = devfn;
+ dummy.path.pci.devfn = devfn;
id = pci_read_config32(&dummy, PCI_VENDOR_ID);
/* Have we found something?
* Some broken boards return 0 if a slot is empty.
@@ -960,8 +960,8 @@
return NULL;
}
devid.type = DEVICE_ID_PCI;
- devid.u.pci.vendor = id & 0xffff;
- devid.u.pci.device = id >> 16;
+ devid.pci.vendor = id & 0xffff;
+ devid.pci.device = id >> 16;
dev = alloc_dev(bus, &dummy.path, &devid);
} else {
/* Enable/disable the device. Once we have found the device
@@ -1013,8 +1013,8 @@
/* Store the interesting information in the device structure. */
dev->id.type = DEVICE_ID_PCI;
- dev->id.u.pci.vendor = id & 0xffff;
- dev->id.u.pci.device = (id >> 16) & 0xffff;
+ dev->id.pci.vendor = id & 0xffff;
+ dev->id.pci.device = (id >> 16) & 0xffff;
dev->hdr_type = hdr_type;
/* Class code, the upper 3 bytes of PCI_CLASS_REVISION. */
dev->class = class >> 8;
Modified: coreboot-v3/device/pci_ops.c
===================================================================
--- coreboot-v3/device/pci_ops.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/pci_ops.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -50,7 +50,7 @@
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read8(PCI_BDEVFN(dev->bus->secondary,
- dev->path.u.pci.devfn),
+ dev->path.pci.devfn),
where);
}
@@ -58,7 +58,7 @@
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read16(PCI_BDEVFN(dev->bus->secondary,
- dev->path.u.pci.devfn),
+ dev->path.pci.devfn),
where);
}
@@ -66,7 +66,7 @@
{
struct bus *pbus = get_pbus(dev);
return ops_pci_bus(pbus)->read32(PCI_BDEVFN(dev->bus->secondary,
- dev->path.u.pci.devfn),
+ dev->path.pci.devfn),
where);
}
@@ -74,7 +74,7 @@
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write8(PCI_BDEVFN(dev->bus->secondary,
- dev->path.u.pci.devfn),
+ dev->path.pci.devfn),
where, val);
}
@@ -82,7 +82,7 @@
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write16(PCI_BDEVFN(dev->bus->secondary,
- dev->path.u.pci.devfn),
+ dev->path.pci.devfn),
where, val);
}
@@ -90,6 +90,6 @@
{
struct bus *pbus = get_pbus(dev);
ops_pci_bus(pbus)->write32(PCI_BDEVFN(dev->bus->secondary,
- dev->path.u.pci.devfn),
+ dev->path.pci.devfn),
where, val);
}
Modified: coreboot-v3/device/pci_rom.c
===================================================================
--- coreboot-v3/device/pci_rom.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/pci_rom.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -45,8 +45,8 @@
* or readonly.
*/
init_archive(&archive);
- sprintf(pcifile, "pci%04x,%04x.rom", dev->id.u.pci.vendor,
- dev->id.u.pci.device);
+ sprintf(pcifile, "pci%04x,%04x.rom", dev->id.pci.vendor,
+ dev->id.pci.device);
ret = find_file(&archive, pcifile, &result);
if (ret) {
@@ -108,7 +108,7 @@
printk(BIOS_SPEW, "PCI ROM Image, Vendor %04x, Device %04x,\n",
rom_data->vendor, rom_data->device);
- if (dev->id.u.pci.vendor != rom_data->vendor || dev->id.u.pci.device !=
rom_data->device) {
+ if (dev->id.pci.vendor != rom_data->vendor || dev->id.pci.device !=
rom_data->device) {
printk(BIOS_ERR,
"Device or Vendor ID mismatch Vendor %04x, Device
%04x\n",
rom_data->vendor, rom_data->device);
Modified: coreboot-v3/device/pcie_device.c
===================================================================
--- coreboot-v3/device/pcie_device.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/pcie_device.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -42,8 +42,8 @@
struct device *child;
max = pci_scan_bus(bus, min_devfn, max_devfn, max);
for (child = bus->children; child; child = child->sibling) {
- if ((child->path.u.pci.devfn < min_devfn) ||
- (child->path.u.pci.devfn > max_devfn)) {
+ if ((child->path.pci.devfn < min_devfn) ||
+ (child->path.pci.devfn > max_devfn)) {
continue;
}
pcie_tune_dev(child);
Modified: coreboot-v3/device/pcix_device.c
===================================================================
--- coreboot-v3/device/pcix_device.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/pcix_device.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -66,8 +66,8 @@
struct device *child;
max = pci_scan_bus(bus, min_devfn, max_devfn, max);
for (child = bus->children; child; child = child->sibling) {
- if ((child->path.u.pci.devfn < min_devfn) ||
- (child->path.u.pci.devfn > max_devfn)) {
+ if ((child->path.pci.devfn < min_devfn) ||
+ (child->path.pci.devfn > max_devfn)) {
continue;
}
pcix_tune_dev(child);
Modified: coreboot-v3/device/pnp_device.c
===================================================================
--- coreboot-v3/device/pnp_device.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/device/pnp_device.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -32,19 +32,19 @@
void pnp_write_config(struct device *dev, u8 reg, u8 value)
{
- outb(reg, dev->path.u.pnp.port);
- outb(value, dev->path.u.pnp.port + 1);
+ outb(reg, dev->path.pnp.port);
+ outb(value, dev->path.pnp.port + 1);
}
u8 pnp_read_config(struct device *dev, u8 reg)
{
- outb(reg, dev->path.u.pnp.port);
- return inb(dev->path.u.pnp.port + 1);
+ outb(reg, dev->path.pnp.port);
+ return inb(dev->path.pnp.port + 1);
}
void pnp_set_logical_device(struct device *dev)
{
- pnp_write_config(dev, 0x07, dev->path.u.pnp.device);
+ pnp_write_config(dev, 0x07, dev->path.pnp.device);
}
void pnp_set_enable(struct device *dev, int enable)
@@ -238,11 +238,11 @@
int i;
path.type = DEVICE_PATH_PNP;
- path.u.pnp.port = base_dev->path.u.pnp.port;
+ path.pnp.port = base_dev->path.pnp.port;
/* Setup the ops and resources on the newly allocated devices. */
for (i = 0; i < functions; i++) {
- path.u.pnp.device = info[i].function;
+ path.pnp.device = info[i].function;
dev = alloc_find_dev(base_dev->bus, &path, &id);
/* Don't initialize a device multiple times. */
Modified: coreboot-v3/include/device/device.h
===================================================================
--- coreboot-v3/include/device/device.h 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/include/device/device.h 2008-08-10 00:20:24 UTC (rev 730)
@@ -108,7 +108,7 @@
struct apic_cluster_id apic_cluster;
struct cpu_id cpu;
struct cpu_bus_id cpu_bus;
- } u;
+ };
};
Modified: coreboot-v3/include/device/path.h
===================================================================
--- coreboot-v3/include/device/path.h 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/include/device/path.h 2008-08-10 00:20:24 UTC (rev 730)
@@ -100,7 +100,7 @@
struct cpu_path cpu;
struct cpu_bus_path cpu_bus;
struct ioport_path ioport;
- } u;
+ };
};
Modified: coreboot-v3/mainboard/emulation/qemu-x86/vga.c
===================================================================
--- coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-08-09 21:03:57 UTC
(rev 729)
+++ coreboot-v3/mainboard/emulation/qemu-x86/vga.c 2008-08-10 00:20:24 UTC
(rev 730)
@@ -44,7 +44,7 @@
struct device_operations qemuvga_pci_ops_dev = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
+ {.pci = {.vendor = PCI_VENDOR_ID_CIRRUS,
.device = PCI_DEVICE_ID_CIRRUS_5446}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
Modified: coreboot-v3/northbridge/amd/geodelx/geodelx.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-08-09 21:03:57 UTC
(rev 729)
+++ coreboot-v3/northbridge/amd/geodelx/geodelx.c 2008-08-10 00:20:24 UTC
(rev 730)
@@ -224,7 +224,7 @@
/** Operations for when the northbridge is running a PCI domain. */
struct device_operations geodelx_north_domain = {
.id = {.type = DEVICE_ID_PCI_DOMAIN,
- .u = {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
+ {.pci_domain = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.constructor = default_device_constructor,
.phase2_setup_scan_bus = geodelx_pci_domain_phase2,
@@ -239,7 +239,7 @@
/** Operations for when the northbridge is running an APIC cluster. */
struct device_operations geodelx_north_apic = {
.id = {.type = DEVICE_ID_APIC_CLUSTER,
- .u = {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
+ {.apic_cluster = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
@@ -257,7 +257,7 @@
*/
struct device_operations geodelx_north_pci = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+ {.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_LXBRIDGE}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
Modified: coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c
===================================================================
--- coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-09
21:03:57 UTC (rev 729)
+++ coreboot-v3/northbridge/intel/i440bxemulation/i440bx.c 2008-08-10
00:20:24 UTC (rev 730)
@@ -68,7 +68,7 @@
/* See mainboard/emulation/qemu-x86 for an example of how these are used. */
struct device_operations i440bx_domain = {
.id = {.type = DEVICE_ID_PCI_DOMAIN,
- .u = {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
+ {.pci_domain = {.vendor = 0x8086,.device = 0x7190}}},
.constructor = default_device_constructor,
.phase3_scan = pci_domain_scan_bus,
.phase4_read_resources = pci_domain_read_resources,
Modified: coreboot-v3/southbridge/amd/cs5536/cs5536.c
===================================================================
--- coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-09 21:03:57 UTC (rev
729)
+++ coreboot-v3/southbridge/amd/cs5536/cs5536.c 2008-08-10 00:20:24 UTC (rev
730)
@@ -696,7 +696,7 @@
struct device_operations cs5536_ops = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+ {.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_CS5536_ISA}}},
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
@@ -708,7 +708,7 @@
struct device_operations cs5536_ide = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = PCI_VENDOR_ID_AMD,
+ {.pci = {.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_AMD_CS5536_B0_IDE}}},
.constructor = default_device_constructor,
#warning FIXME: what has to go in phase3_scan?
Modified: coreboot-v3/southbridge/intel/i82371eb/i82371eb.c
===================================================================
--- coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-08-09 21:03:57 UTC
(rev 729)
+++ coreboot-v3/southbridge/intel/i82371eb/i82371eb.c 2008-08-10 00:20:24 UTC
(rev 730)
@@ -85,7 +85,7 @@
/* You can override or extend each operation as needed for the device. */
struct device_operations i82371eb_isa = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = 0x8086,.device = 0x7000}}},
+ {.pci = {.vendor = 0x8086,.device = 0x7000}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
@@ -98,7 +98,7 @@
struct device_operations i82371eb_ide = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = 0x8086,.device = 0x7010}}},
+ {.pci = {.vendor = 0x8086,.device = 0x7010}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
@@ -111,7 +111,7 @@
struct device_operations i82371eb_acpi = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = 0x8086,.device = 0x7113}}},
+ {.pci = {.vendor = 0x8086,.device = 0x7113}}},
.constructor = default_device_constructor,
.phase3_scan = 0,
.phase4_read_resources = pci_dev_read_resources,
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-09 21:03:57 UTC
(rev 729)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-10 00:20:24 UTC
(rev 730)
@@ -45,10 +45,11 @@
/* the range makes it hard to use the library function. Sorry.
* I realize this is not pretty. It would be nice if we could
* use anonymous unions.
+ * We now use anonymous unions. Fix up the code?
*/
- if ((lpc_dev->id.u.pci.vendor != PCI_VENDOR_ID_NVIDIA) || (
- (lpc_dev->id.u.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
- (lpc_dev->id.u.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
+ if ((lpc_dev->id.pci.vendor != PCI_VENDOR_ID_NVIDIA) || (
+ (lpc_dev->id.pci.device < PCI_DEVICE_ID_NVIDIA_MCP55_LPC) ||
+ (lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
) ) {
u32 id;
id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
@@ -80,16 +81,16 @@
unsigned devfn;
/* sorry. Again, anonymous unions etc. would make this easier. */
- if(dev->id.u.pci.device==0x0000) {
+ if(dev->id.pci.device==0x0000) {
vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
deviceid = (vendorid>>16) & 0xffff;
// vendorid &= 0xffff;
} else {
// vendorid = dev->vendor;
- deviceid = dev->id.u.pci.device;
+ deviceid = dev->id.pci.device;
}
- devfn = (dev->path.u.pci.devfn) & ~7;
+ devfn = (dev->path.pci.devfn) & ~7;
switch(deviceid) {
case PCI_DEVICE_ID_NVIDIA_MCP55_HT:
return;
@@ -129,7 +130,7 @@
case PCI_DEVICE_ID_NVIDIA_MCP55_SATA1: //three
devfn -= (4<<3);
index = 22;
- i = (dev->path.u.pci.devfn) & 7;
+ i = (dev->path.pci.devfn) & 7;
if(i>0) {
index -= (i+3);
}
@@ -249,7 +250,7 @@
struct device_operations nvidia_ops = {
.id = {.type = DEVICE_ID_PCI,
- .u = {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
+ {.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_PCI}}},
.constructor = default_device_constructor,
.phase3_scan = scan_static_bus,
Modified: coreboot-v3/superio/fintek/f71805f/superio.c
===================================================================
--- coreboot-v3/superio/fintek/f71805f/superio.c 2008-08-09 21:03:57 UTC
(rev 729)
+++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-08-10 00:20:24 UTC
(rev 730)
@@ -41,12 +41,12 @@
static void pnp_enter_conf_state(struct device *dev)
{
- outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.pnp.port);
}
static void pnp_exit_conf_state(struct device *dev)
{
- outb(0xaa, dev->path.u.pnp.port);
+ outb(0xaa, dev->path.pnp.port);
}
void f71805f_pnp_set_resources(struct device *dev)
@@ -79,7 +79,7 @@
if (!dev->enabled)
return;
- switch (dev->path.u.pnp.device) {
+ switch (dev->path.pnp.device) {
case F71805F_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
//TODO: needed? fix or remove?
Modified: coreboot-v3/superio/ite/it8716f/superio.c
===================================================================
--- coreboot-v3/superio/ite/it8716f/superio.c 2008-08-09 21:03:57 UTC (rev
729)
+++ coreboot-v3/superio/ite/it8716f/superio.c 2008-08-10 00:20:24 UTC (rev
730)
@@ -37,14 +37,14 @@
/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
static void pnp_enter_ext_func_mode(struct device *dev)
{
- outb(0x87, dev->path.u.pnp.port);
- outb(0x01, dev->path.u.pnp.port);
- outb(0x55, dev->path.u.pnp.port);
+ outb(0x87, dev->path.pnp.port);
+ outb(0x01, dev->path.pnp.port);
+ outb(0x55, dev->path.pnp.port);
- if (dev->path.u.pnp.port == 0x4e) {
- outb(0xaa, dev->path.u.pnp.port);
+ if (dev->path.pnp.port == 0x4e) {
+ outb(0xaa, dev->path.pnp.port);
} else {
- outb(0x55, dev->path.u.pnp.port);
+ outb(0x55, dev->path.pnp.port);
}
}
@@ -142,7 +142,7 @@
conf = dev->device_configuration;
/* TODO: FDC, PP, KBCM, MIDI, GAME, IR. */
- switch (dev->path.u.pnp.device) {
+ switch (dev->path.pnp.device) {
case IT8716F_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
// init_uart8250(res0->base, &conf->com1);
Modified: coreboot-v3/superio/winbond/w83627hf/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-08-09 21:03:57 UTC
(rev 729)
+++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-08-10 00:20:24 UTC
(rev 730)
@@ -36,13 +36,13 @@
static void pnp_enter_ext_func_mode(struct device * dev)
{
- outb(0x87, dev->path.u.pnp.port);
- outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.pnp.port);
+ outb(0x87, dev->path.pnp.port);
}
static void pnp_exit_ext_func_mode(struct device * dev)
{
- outb(0xaa, dev->path.u.pnp.port);
+ outb(0xaa, dev->path.pnp.port);
}
static void pnp_write_index(u16 port_base, u8 reg, u8 value)
@@ -73,7 +73,7 @@
#warning Fix CMOS handling
// get_option(&power_on, "power_on_after_fail");
pnp_enter_ext_func_mode(dev);
- pnp_write_index(dev->path.u.pnp.port,7,0x0a);
+ pnp_write_index(dev->path.pnp.port,7,0x0a);
value = pnp_read_config(dev, 0xE4);
value &= ~(3<<5);
if(power_on) {
@@ -128,7 +128,7 @@
}
conf = dev->device_configuration;
- switch(dev->path.u.pnp.device) {
+ switch(dev->path.pnp.device) {
case W83627HF_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
#warning init_uart8250
@@ -167,7 +167,7 @@
{
pnp_enter_ext_func_mode(dev);
pnp_enable_resources(dev);
- switch(dev->path.u.pnp.device) {
+ switch(dev->path.pnp.device) {
case W83627HF_HWM:
printk(BIOS_DEBUG, "w83627hf hwm smbus enabled\n");
enable_hwm_smbus(dev);
Modified: coreboot-v3/util/dtc/flattree.c
===================================================================
--- coreboot-v3/util/dtc/flattree.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/util/dtc/flattree.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -551,19 +551,19 @@
if (path && path[1]) {
path++;
if (!strncmp(tree->name, "cpu", 3)){
- fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,.u={.cpu={
.id = 0x%s }}},\n",
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_CPU,{.cpu={
.id = 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "bus", 3)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_BUS,.u={.pci_bus={ .bus = 0x%s }}},\n",
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_BUS,{.pci_bus={ .bus = 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "apic", 4)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_APIC,.u={.apic={ 0x%s }}},\n",
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_APIC,{.apic={
0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "domain", 6)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_DOMAIN,.u={.pci_domain={ .domain = 0x%s }}},\n",
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x%s }}},\n",
path);
}
if (!strncmp(tree->name, "pci", 3)){
@@ -580,11 +580,11 @@
else
fn = "0";
- fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,.u={.pci={
.devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n",
+ fprintf(f, "\t.path = {.type=DEVICE_PATH_PCI,{.pci={
.devfn = PCI_DEVFN(0x%s, 0x%s)}}},\n",
dev, fn);
}
if (!strncmp(tree->name, "ioport", 6)){
- fprintf(f, "\t.path =
{.type=DEVICE_PATH_IOPORT,.u={.ioport={.iobase=0x%s}}},\n",
+ fprintf(f, "\t.path =
{.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x%s}}},\n",
path);
}
}
Modified: coreboot-v3/util/x86emu/biosemu.c
===================================================================
--- coreboot-v3/util/x86emu/biosemu.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/util/x86emu/biosemu.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -323,7 +323,7 @@
int i;
unsigned short initialcs = (addr & 0xF0000) >> 4;
unsigned short initialip = (addr + 3) & 0xFFFF;
- unsigned short devfn = dev->bus->secondary << 8 | dev->path.u.pci.devfn;
+ unsigned short devfn = dev->bus->secondary << 8 | dev->path.pci.devfn;
X86EMU_intrFuncs intFuncs[256];
X86EMU_setMemBase(0, 0x100000);
Modified: coreboot-v3/util/x86emu/pcbios/pcibios.c
===================================================================
--- coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-08-09 21:03:57 UTC (rev
729)
+++ coreboot-v3/util/x86emu/pcbios/pcibios.c 2008-08-10 00:20:24 UTC (rev
730)
@@ -64,7 +64,7 @@
dev = dev_find_pci_device(X86_DX, X86_CX, dev);
if (dev != 0) {
X86_BH = dev->bus->secondary;
- X86_BL = dev->path.u.pci.devfn;
+ X86_BL = dev->path.pci.devfn;
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
@@ -79,7 +79,7 @@
dev = dev_find_class(X86_ECX, dev);
if (dev != 0) {
X86_BH = dev->bus->secondary;
- X86_BL = dev->path.u.pci.devfn;
+ X86_BL = dev->path.pci.devfn;
X86_AH = SUCCESSFUL;
X86_EFLAGS &= ~FB_CF; /* clear carry flag */
ret = 1;
Modified: coreboot-v3/util/x86emu/vm86.c
===================================================================
--- coreboot-v3/util/x86emu/vm86.c 2008-08-09 21:03:57 UTC (rev 729)
+++ coreboot-v3/util/x86emu/vm86.c 2008-08-10 00:20:24 UTC (rev 730)
@@ -249,7 +249,7 @@
*(unsigned char *) i = 0;
}
- real_mode_switch_call_vga((dev->bus->secondary << 8) |
dev->path.u.pci.devfn);
+ real_mode_switch_call_vga((dev->bus->secondary << 8) |
dev->path.pci.devfn);
}
@@ -603,7 +603,7 @@
// busnum is an unsigned char;
// devfn is an int, so we mask it off.
busdevfn = (dev->bus->secondary << 8)
- | (dev->path.u.pci.devfn & 0xff);
+ | (dev->path.pci.devfn & 0xff);
printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
busdevfn);
*pebx = busdevfn;
retval = 0;
--
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