Move mcp55 subsystem ID setting to the v3 model.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Arbeitskopie)
@@ -22,6 +22,8 @@
#ifndef MCP55_H
#define MCP55_H
+void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device);
+struct pci_operations mcp55_pci_dev_ops_pci;
-
#endif /* MCP55_H */
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Arbeitskopie)
@@ -68,12 +68,6 @@
#ifdef CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
-
-#warning set subsystem id on mcp55 ide
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_ide = {
@@ -86,6 +80,6 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Arbeitskopie)
@@ -44,11 +44,6 @@
dword = pci_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
-#warning mange set subsystem in mcp55 usb2
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
static void usb2_set_resources(struct device *dev)
@@ -84,5 +79,5 @@
.phase4_set_resources = usb2_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb2_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Arbeitskopie)
@@ -67,13 +67,6 @@
dword = pci_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
-
-
-#warning finish set subsystem in mcp55 sata
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_sata = {
@@ -86,5 +79,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Arbeitskopie)
@@ -34,11 +34,6 @@
static void usb_init(struct device * dev)
{
-#warning handle subsystem set in mcp55 usb
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_usb = {
@@ -51,5 +46,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie)
@@ -248,6 +248,18 @@
}
+void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
+{
+ pci_write_config32(dev, PCI_CB_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+/** MCP55 specific device operation for PCI devices. */
+struct pci_operations mcp55_pci_dev_ops_pci = {
+ .set_subsystem = mcp55_pci_dev_set_subsystem,
+};
+
struct device_operations nvidia_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Arbeitskopie)
@@ -127,24 +127,19 @@
if (res)
pm_base = res->base;
#endif
-#warning finish subsystem set in mcp55 smbus
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_smbus = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}},
- .constructor = default_device_constructor,
- .phase3_scan = scan_static_bus,
+ .constructor = default_device_constructor,
+ .phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_sm_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
- .phase6_init = mcp55_sm_init,
- .ops_pci = &pci_dev_ops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
+ .phase6_init = mcp55_sm_init,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
+ .ops_smbus_bus = &lops_smbus_bus,
};
--
http://www.hailfinger.org/
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.h (Arbeitskopie)
@@ -22,6 +22,8 @@
#ifndef MCP55_H
#define MCP55_H
+void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device);
+struct pci_operations mcp55_pci_dev_ops_pci;
-
#endif /* MCP55_H */
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/ide.c (Arbeitskopie)
@@ -68,12 +68,6 @@
#ifdef CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
-
-#warning set subsystem id on mcp55 ide
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_ide = {
@@ -86,6 +80,6 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb2.c (Arbeitskopie)
@@ -44,11 +44,6 @@
dword = pci_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
-#warning mange set subsystem in mcp55 usb2
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
static void usb2_set_resources(struct device *dev)
@@ -84,5 +79,5 @@
.phase4_set_resources = usb2_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb2_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/sata.c (Arbeitskopie)
@@ -67,13 +67,6 @@
dword = pci_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
-
-
-#warning finish set subsystem in mcp55 sata
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_sata = {
@@ -86,5 +79,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/usb.c (Arbeitskopie)
@@ -34,11 +34,6 @@
static void usb_init(struct device * dev)
{
-#warning handle subsystem set in mcp55 usb
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_usb = {
@@ -51,5 +46,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/mcp55.c (Arbeitskopie)
@@ -248,6 +248,18 @@
}
+void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
+{
+ pci_write_config32(dev, PCI_CB_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+/** MCP55 specific device operation for PCI devices. */
+struct pci_operations mcp55_pci_dev_ops_pci = {
+ .set_subsystem = mcp55_pci_dev_set_subsystem,
+};
+
struct device_operations nvidia_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
Index: corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c
===================================================================
--- corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Revision 749)
+++ corebootv3-mcp55_subsystem/southbridge/nvidia/mcp55/smbus.c (Arbeitskopie)
@@ -127,24 +127,19 @@
if (res)
pm_base = res->base;
#endif
-#warning finish subsystem set in mcp55 smbus
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_smbus = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}},
- .constructor = default_device_constructor,
- .phase3_scan = scan_static_bus,
+ .constructor = default_device_constructor,
+ .phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_sm_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
- .phase6_init = mcp55_sm_init,
- .ops_pci = &pci_dev_ops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
+ .phase6_init = mcp55_sm_init,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
+ .ops_smbus_bus = &lops_smbus_bus,
};
--
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