Author: rminnich
Date: 2008-08-13 04:44:46 +0200 (Wed, 13 Aug 2008)
New Revision: 753
Modified:
coreboot-v3/arch/x86/Kconfig
coreboot-v3/arch/x86/Makefile
coreboot-v3/arch/x86/resourcemap.c
Log:
The change to Kconfig is self-acked.
Add a depend clause so that we don't see these things on Geode.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
The other changes are:
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/Kconfig
===================================================================
--- coreboot-v3/arch/x86/Kconfig 2008-08-13 02:41:29 UTC (rev 752)
+++ coreboot-v3/arch/x86/Kconfig 2008-08-13 02:44:46 UTC (rev 753)
@@ -133,6 +133,7 @@
config IOAPIC
boolean
+ depends ARCH_X86
default 0
help
If you want to configure an IOAPIC, set this.
@@ -209,5 +210,6 @@
config APIC_ID_OFFSET
hex "APIC ID offset"
default 0x10
+ depends IO_APIC
help
This is entirely mainboard dependent. 0x10 is a *typical*
setting but not always a good setting.
Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile 2008-08-13 02:41:29 UTC (rev 752)
+++ coreboot-v3/arch/x86/Makefile 2008-08-13 02:44:46 UTC (rev 753)
@@ -183,7 +183,7 @@
compute_ip_checksum.c string.c
STAGE2_ARCH_X86_SRC = archtables.c coreboot_table.c udelay_io.c
-STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c
STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
ifeq ($(CONFIG_PIRQ_TABLE),y)
Modified: coreboot-v3/arch/x86/resourcemap.c
===================================================================
--- coreboot-v3/arch/x86/resourcemap.c 2008-08-13 02:41:29 UTC (rev 752)
+++ coreboot-v3/arch/x86/resourcemap.c 2008-08-13 02:44:46 UTC (rev 753)
@@ -47,8 +47,6 @@
/* NOTE: By doing the config write in this manner we guarantee that this
* will work in stage1 or stage2.
*/
-#define pci_read_config32(busdevfn, where) pci_cf8_conf1.read32(busdevfn,
where)
-#define pci_write_config32(busdevfn, where, what)
pci_cf8_conf1.write32(busdevfn, where, what)
void setup_resource_map_x_offset(const struct rmap *rm, u32 max,
u32 offset_bdf, u32 offset_pciio,
@@ -77,10 +75,10 @@
dev <<= 3;
dev |= rm->pcm.fn;
dev += offset_devfn;
- reg = pci_read_config32(PCI_BDEVFN(rm->pcm.bus +
offset_bus, dev), where);
+ reg = pci_conf1_read_config32(PCI_BDEVFN(rm->pcm.bus
+ offset_bus, dev), where);
reg &= rm->pcm.and;
reg |= rm->pcm.or + offset_pciio;
- pci_write_config32(PCI_BDEVFN(rm->pcm.bus +
offset_bus, dev), where, reg);
+ pci_conf1_write_config32(PCI_BDEVFN(rm->pcm.bus +
offset_bus, dev), where, reg);
}
break;
case TIO8:
--
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