no good deed goes unpunished; thanks to your reviews and acks, I have one more patch :-)
ron
Add Kconfig variables needed for new platforms. Add smbus ops to stage 2. Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]> Index: device/Kconfig =================================================================== --- device/Kconfig (revision 753) +++ device/Kconfig (working copy) @@ -95,5 +95,19 @@ help Enable support for Suspend-to-RAM (S3) functionality. +config PCI_64BIT_PREF_MEM + bool "64 bit prefetchable memory addresses" + help + Enable support for 64-bit prefetchable memory addresses in PCI. + +config HW_MEM_HOLE_SIZEK + hex "HW memory hole size in KB" + default 0x1000 + help + Some chipsets support setting up a "hole" at the top of memory. It is essentially + a hole torn in the physical address space so that you can fit non-memory resources + (e.g. flash) at the top of the 4G address space. Given that this only happens on machines + with lots of memory, the default 4 MB is a very reasonable value. + + endmenu - Index: device/Makefile =================================================================== --- device/Makefile (revision 753) +++ device/Makefile (working copy) @@ -25,5 +25,6 @@ $(Q)$(CC) $(INITCFLAGS) -c $< -o $@ STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \ - pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c + pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c \ + smbus_ops.c
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