Author: hailfinger
Date: 2008-08-14 11:37:46 +0200 (Thu, 14 Aug 2008)
New Revision: 762
Modified:
coreboot-v3/southbridge/nvidia/mcp55/ide.c
coreboot-v3/southbridge/nvidia/mcp55/lpc.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
coreboot-v3/southbridge/nvidia/mcp55/pci.c
coreboot-v3/southbridge/nvidia/mcp55/pcie.c
coreboot-v3/southbridge/nvidia/mcp55/sata.c
coreboot-v3/southbridge/nvidia/mcp55/smbus.c
coreboot-v3/southbridge/nvidia/mcp55/usb.c
coreboot-v3/southbridge/nvidia/mcp55/usb2.c
Log:
Use the correct MCP55 PCI subsystem ID setting function.
This fixes a genuine bug in the MCP55 code.
Moving this away from PCI ops is the next goal.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -68,12 +68,6 @@
#ifdef CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
-
-#warning set subsystem id on mcp55 ide
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_ide = {
@@ -86,6 +80,6 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = ide_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -338,13 +338,6 @@
mcp55_lpc_enable_childrens_resources(dev);
}
-/* This is awaiting the subsystem support in dtc/dts
-static void lpci_set_subsystem(struct device *dev, unsigned vendor, unsigned
device)
-{
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-}
-*/
struct device_operations mcp55_lpc = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
@@ -355,7 +348,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_pro = {
@@ -368,7 +361,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_lpc2 = {
@@ -381,7 +374,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_lpc3 = {
@@ -394,7 +387,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_lpc4 = {
@@ -407,7 +400,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_lpc5 = {
@@ -420,7 +413,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_lpc6 = {
@@ -433,7 +426,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = mcp55_lpc_enable_resources,
.phase6_init = lpc_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_lpcslave = {
@@ -446,5 +439,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = lpc_slave_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-14 09:28:28 UTC
(rev 761)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-08-14 09:37:46 UTC
(rev 762)
@@ -248,6 +248,18 @@
}
+void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device)
+{
+ pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
+ ((device & 0xffff) << 16) | (vendor & 0xffff));
+}
+
+/** MCP55 specific device operation for PCI devices. */
+struct pci_operations mcp55_pci_dev_ops_pci = {
+ .set_subsystem = mcp55_pci_dev_set_subsystem,
+};
+
struct device_operations nvidia_ops = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.h
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-08-14 09:28:28 UTC
(rev 761)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.h 2008-08-14 09:37:46 UTC
(rev 762)
@@ -22,6 +22,10 @@
#ifndef MCP55_H
#define MCP55_H
+#define PCI_MCP55_SUBSYSTEM_VENDOR_ID 0x40
+void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
+ unsigned int device);
+struct pci_operations mcp55_pci_dev_ops_pci;
#endif /* MCP55_H */
Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -99,5 +99,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pci_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -57,7 +57,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_pcie_b_c = {
@@ -71,7 +71,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_pcie_d = {
@@ -85,7 +85,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_pcie_e = {
@@ -99,7 +99,7 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
struct device_operations mcp55_pcie_f = {
@@ -113,5 +113,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_bus_enable_resources,
.phase6_init = pcie_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -67,13 +67,6 @@
dword = pci_read_config32(dev, 0xf8);
dword |= 2;
pci_write_config32(dev, 0xf8, dword);
-
-
-#warning finish set subsystem in mcp55 sata
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_sata = {
@@ -86,5 +79,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = sata_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/smbus.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/smbus.c 2008-08-14 09:28:28 UTC
(rev 761)
+++ coreboot-v3/southbridge/nvidia/mcp55/smbus.c 2008-08-14 09:37:46 UTC
(rev 762)
@@ -127,24 +127,19 @@
if (res)
pm_base = res->base;
#endif
-#warning finish subsystem set in mcp55 smbus
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_smbus = {
.id = {.type = DEVICE_ID_PCI,
{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
.device = PCI_DEVICE_ID_NVIDIA_MCP55_SM2}}},
- .constructor = default_device_constructor,
- .phase3_scan = scan_static_bus,
+ .constructor = default_device_constructor,
+ .phase3_scan = scan_static_bus,
.phase4_read_resources = mcp55_sm_read_resources,
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
- .phase6_init = mcp55_sm_init,
- .ops_pci = &pci_dev_ops_pci,
- .ops_smbus_bus = &lops_smbus_bus,
+ .phase6_init = mcp55_sm_init,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
+ .ops_smbus_bus = &lops_smbus_bus,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/usb.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/usb.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/usb.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -34,11 +34,6 @@
static void usb_init(struct device * dev)
{
-#warning handle subsystem set in mcp55 usb
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
struct device_operations mcp55_usb = {
@@ -51,5 +46,5 @@
.phase4_set_resources = pci_dev_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-08-14 09:28:28 UTC (rev
761)
+++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-08-14 09:37:46 UTC (rev
762)
@@ -44,11 +44,6 @@
dword = pci_read_config32(dev, 0xf8);
dword |= 40;
pci_write_config32(dev, 0xf8, dword);
-#warning mange set subsystem in mcp55 usb2
-#if 0
- pci_write_config32(dev, 0x40,
- ((device & 0xffff) << 16) | (vendor & 0xffff));
-#endif
}
static void usb2_set_resources(struct device *dev)
@@ -84,5 +79,5 @@
.phase4_set_resources = usb2_set_resources,
.phase5_enable_resources = pci_dev_enable_resources,
.phase6_init = usb2_init,
- .ops_pci = &pci_dev_ops_pci,
+ .ops_pci = &mcp55_pci_dev_ops_pci,
};
--
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