Author: hailfinger
Date: 2008-08-15 21:56:41 +0200 (Fri, 15 Aug 2008)
New Revision: 770
Modified:
coreboot-v3/mainboard/gigabyte/m57sli/Makefile
Log:
arch/x86/pci_ops_conf1.c is already linked into stage1 and SHARED.
Don't link it into initram as well.
With this change, I can compile stage0, stage1, initram and large parts
of stage2 without problems for the M57SLI target.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-15 19:23:11 UTC
(rev 769)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-15 19:56:41 UTC
(rev 770)
@@ -28,7 +28,6 @@
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
- $(src)/arch/x86/pci_ops_conf1.c \
$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
$(src)/lib/clog2.c
--
coreboot mailing list
[email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
