Author: hailfinger
Date: 2008-08-22 21:42:45 +0200 (Fri, 22 Aug 2008)
New Revision: 806
Modified:
coreboot-v3/arch/x86/amd/stage0.S
Log:
Improve comments in Fam10h CAR.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S 2008-08-22 18:24:53 UTC (rev 805)
+++ coreboot-v3/arch/x86/amd/stage0.S 2008-08-22 19:42:45 UTC (rev 806)
@@ -180,10 +180,10 @@
/* for GH, CAR need to set DRAM Base/Limit Registers to direct that to
node0 */
/* Only BSP needed, for other nodes set during HT/memory init. */
- /* So we need to check if it is BSP */
- movl $0x1b, %ecx
+ /* So we need to check if it is BSP/BSC */
+ movl $0x1b, %ecx /* APIC Base Address Register */
rdmsr
- bt $8, %eax /*BSC */
+ bt $8, %eax /* BSC Boot Strap CPU Core */
jnc CAR_FAM10_out
/* Enable RT tables on BSP */
@@ -341,10 +341,10 @@
#ifdef CONFIG_CPU_AMD_K10
- /* So we need to check if it is BSP */
- movl $0x1b, %ecx
+ /* So we need to check if it is BSP/BSC */
+ movl $0x1b, %ecx /* APIC BAR */
rdmsr
- bt $8, %eax /*BSC */
+ bt $8, %eax /* BSC */
jnc CAR_FAM10_ap
#endif
--
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