Author: rminnich
Date: 2008-08-23 18:51:00 +0200 (Sat, 23 Aug 2008)
New Revision: 807
Modified:
coreboot-v3/arch/x86/stage1.c
coreboot-v3/include/arch/x86/amd/k8/k8.h
coreboot-v3/include/lib.h
coreboot-v3/lib/delay.c
coreboot-v3/mainboard/amd/serengeti/Makefile
coreboot-v3/mainboard/amd/serengeti/mainboard.h
coreboot-v3/mainboard/gigabyte/m57sli/Makefile
coreboot-v3/northbridge/amd/k8/common.c
coreboot-v3/northbridge/amd/k8/domain.c
coreboot-v3/northbridge/amd/k8/pci.c
coreboot-v3/northbridge/amd/k8/raminit.c
Log:
This now compiles and has a simple error on build to stage2.
Geode still builds fine.
include/lib.h includes a new function, cycles(), which is a u64 and
architecture-defined. (Thanks, Plan 9, for a sensible idea).
All rdtsc removed in favor of cycles()
All other changes are k8 specific. None of these changes adversely
impact existing platforms AFAICT.
Goal is that by 31/8/8, we're testing on simnow.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/stage1.c
===================================================================
--- coreboot-v3/arch/x86/stage1.c 2008-08-22 19:42:45 UTC (rev 806)
+++ coreboot-v3/arch/x86/stage1.c 2008-08-23 16:51:00 UTC (rev 807)
@@ -109,6 +109,16 @@
return;
}
+/** cycles
+ * provide 64-bit high precision counter
+ * @returns Time in 64 bits
+ */
+u64 cycles(void)
+{
+ u64 ret;
+ asm volatile ("rdtsc" : "=A" (ret));
+ return ret;
+}
#ifdef CONFIG_PAYLOAD_ELF_LOADER
/* until we get rid of elf */
Modified: coreboot-v3/include/arch/x86/amd/k8/k8.h
===================================================================
--- coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-22 19:42:45 UTC (rev
806)
+++ coreboot-v3/include/arch/x86/amd/k8/k8.h 2008-08-23 16:51:00 UTC (rev
807)
@@ -512,6 +512,8 @@
#define NBCAP_CmpCap_SHIFT 12
#define NBCAP_CmpCap_MASK 3
+/* other hypertransport constants */
+#define HT_INIT_CONTROL 0x6c
#define LinkConnected (1 << 0)
#define InitComplete (1 << 1)
@@ -619,4 +621,12 @@
unsigned get_apicid_base(unsigned ioapic_num);
void amd_sibling_init(struct device *cpu);
+/* memory hole management */
+struct hw_mem_hole_info {
+ unsigned hole_startk;
+ int node_id;
+};
+
+struct hw_mem_hole_info get_hw_mem_hole_info(void);
+
#endif /* ! ASSEMBLY */
Modified: coreboot-v3/include/lib.h
===================================================================
--- coreboot-v3/include/lib.h 2008-08-22 19:42:45 UTC (rev 806)
+++ coreboot-v3/include/lib.h 2008-08-23 16:51:00 UTC (rev 807)
@@ -34,6 +34,12 @@
void mdelay(unsigned int msecs);
void delay(unsigned int secs);
+/* all architectures must implement a 64-bit time counter
+ * that is compiled into stage1
+ * rdtsc is usually fine.
+ */
+u64 cycles(void);
+
void beep_short(void);
void beep_long(void);
Modified: coreboot-v3/lib/delay.c
===================================================================
--- coreboot-v3/lib/delay.c 2008-08-22 19:42:45 UTC (rev 806)
+++ coreboot-v3/lib/delay.c 2008-08-23 16:51:00 UTC (rev 807)
@@ -18,6 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
*/
+#include <types.h>
#include <lib.h>
void mdelay(unsigned int msecs)
Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-08-22 19:42:45 UTC
(rev 806)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-08-23 16:51:00 UTC
(rev 807)
@@ -31,6 +31,7 @@
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
+ $(src)/northbridge/amd/k8/dqs.c \
$(src)/arch/x86/pci_ops_conf1.c \
$(src)/southbridge/amd/amd8111/stage1_smbus.c \
$(src)/lib/clog2.c
Modified: coreboot-v3/mainboard/amd/serengeti/mainboard.h
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-22 19:42:45 UTC
(rev 806)
+++ coreboot-v3/mainboard/amd/serengeti/mainboard.h 2008-08-23 16:51:00 UTC
(rev 807)
@@ -22,4 +22,5 @@
*/
#define CPU_SOCKET_TYPE SOCKET_AM2
-#define MEM_TRAIN_SEQ 1 /* for now */
+#define MEM_TRAIN_SEQ 0 /* for now */
+#define HW_MEM_HOLE_SIZE_AUTO_INC 0
Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-22 19:42:45 UTC
(rev 806)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile 2008-08-23 16:51:00 UTC
(rev 807)
@@ -28,6 +28,7 @@
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
+ $(src)/northbridge/amd/k8/dqs.c \
$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
$(src)/lib/clog2.c
Modified: coreboot-v3/northbridge/amd/k8/common.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/common.c 2008-08-22 19:42:45 UTC (rev
806)
+++ coreboot-v3/northbridge/amd/k8/common.c 2008-08-23 16:51:00 UTC (rev
807)
@@ -45,10 +45,11 @@
#include <lib.h>
#include <lapic.h>
+/*
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
#include <cpu/amd/model_fxx_rev.h>
#endif
-
+*/
struct amdk8_sysconf sysconf;
#define FX_DEVS 8
@@ -116,11 +117,6 @@
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-struct hw_mem_hole_info {
- unsigned hole_startk;
- int node_id;
-};
-
struct hw_mem_hole_info get_hw_mem_hole_info(void)
{
struct hw_mem_hole_info mem_hole;
@@ -215,7 +211,7 @@
}
-static u32 hoist_memory(unsigned long hole_startk, int i)
+u32 hoist_memory(unsigned long hole_startk, int i)
{
int ii;
u32 carry_over;
Modified: coreboot-v3/northbridge/amd/k8/domain.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/domain.c 2008-08-22 19:42:45 UTC (rev
806)
+++ coreboot-v3/northbridge/amd/k8/domain.c 2008-08-23 16:51:00 UTC (rev
807)
@@ -44,8 +44,8 @@
#include <mc146818rtc.h>
#include <lib.h>
#include <lapic.h>
+#include <mainboard.h>
-
#ifdef CONFIG_PCI_64BIT_PREF_MEM
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH)
#endif
@@ -166,8 +166,11 @@
static void k8_pci_domain_set_resources(struct device * dev)
{
+#if CONFIG_HW_MEM_HOLE_SIZEK != 0
struct hw_mem_hole_info get_hw_mem_hole_info(void);
void disable_hoist_memory(unsigned long hole_startk, int i);
+ u32 hoist_memory(unsigned long hole_startk, int i);
+#endif
#if CONFIG_PCI_64BIT_PREF_MEM == 1
struct resource *io, *mem1, *mem2;
struct resource *resource, *last;
Modified: coreboot-v3/northbridge/amd/k8/pci.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/pci.c 2008-08-22 19:42:45 UTC (rev
806)
+++ coreboot-v3/northbridge/amd/k8/pci.c 2008-08-23 16:51:00 UTC (rev
807)
@@ -45,10 +45,6 @@
#include <lib.h>
#include <lapic.h>
-#if CONFIG_HW_MEM_HOLE_SIZEK != 0
-#include <cpu/amd/model_fxx_rev.h>
-#endif
-
#define FX_DEVS 8
extern struct device * __f0_dev[FX_DEVS];
extern struct device * __f1_dev[FX_DEVS];
Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-22 19:42:45 UTC (rev
806)
+++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-08-23 16:51:00 UTC (rev
807)
@@ -60,7 +60,7 @@
#endif
/* bit [10,8] are dev func, bit[1,0] are dev index */
-static u32 pci_read_config32_index(u32 dev, u32 index_reg, u32 index)
+u32 pci_read_config32_index(u32 dev, u32 index_reg, u32 index)
{
u32 dword;
@@ -71,7 +71,7 @@
return dword;
}
-static void pci_write_config32_index(u32 dev, u32 index_reg, u32 index, u32
data)
+void pci_write_config32_index(u32 dev, u32 index_reg, u32 index, u32 data)
{
pci_conf1_write_config32(dev, index_reg, index);
@@ -80,7 +80,7 @@
}
-static u32 pci_read_config32_index_wait(u32 dev, u32 index_reg, u32 index)
+u32 pci_read_config32_index_wait(u32 dev, u32 index_reg, u32 index)
{
u32 dword;
@@ -97,7 +97,7 @@
return dword;
}
-static void pci_write_config32_index_wait(u32 dev, u32 index_reg, u32 index,
u32 data)
+void pci_write_config32_index_wait(u32 dev, u32 index_reg, u32 index, u32 data)
{
u32 dword;
@@ -2685,7 +2685,58 @@
}
#endif
+static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
+{
+ int i;
+ u32 mask = 0;
+ unsigned int needs_reset = 0;
+ void hard_reset(void);
+
+ if(sysinfo->nodes == 1) return; // in case only one cpu installed
+
+ for(i=1; i<sysinfo->nodes; i++) {
+ /* Skip everything if I don't have any memory on this
controller */
+ if(sysinfo->mem_trained[i]==0x00) continue;
+
+ mask |= (1<<i);
+
+ }
+
+ i = 1;
+ while(1) {
+ if(mask & (1<<i)) {
+ if((sysinfo->mem_trained[i])!=0x80) {
+ mask &= ~(1<<i);
+ }
+ }
+
+ if(!mask) break;
+
+ i++;
+ i%=sysinfo->nodes;
+ }
+
+ for(i=0; i<sysinfo->nodes; i++) {
+ printk(BIOS_DEBUG, "mem_trained[%02x]=%02x\n", i,
sysinfo->mem_trained[i]);
+ switch(sysinfo->mem_trained[i]) {
+ case 0: //don't need train
+ case 1: //trained
+ break;
+ case 0x81: //recv1: fail
+ case 0x82: //Pos :fail
+ case 0x83: //recv2: fail
+ needs_reset = 1;
+ break;
+ }
+ }
+ if(needs_reset) {
+ printk(BIOS_DEBUG, "mem trained failed\n");
+ hard_reset();
+ }
+
+}
+
void sdram_enable(int controllers, const struct mem_controller *ctrl, struct
sys_info *sysinfo)
{
int i;
@@ -2868,7 +2919,7 @@
#if MEM_TRAIN_SEQ == 0
- #ifdef
+ #ifdef K8_REV_F_SUPPORT_F0_F1_WORKAROUND
dqs_timing(controllers, ctrl, tsc0, sysinfo);
#else
dqs_timing(controllers, ctrl, sysinfo);
--
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