This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy.
Signed-off-by: Bari Ari <[EMAIL PROTECTED]>
Index: src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r.c (revision 3542)
+++ src/southbridge/via/vt8237r/vt8237r.c (working copy)
@@ -79,8 +79,6 @@
pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
- /* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */
- pci_write_config8(dev, 0x41, 0x7f);
}
struct chip_operations southbridge_via_vt8237r_ops = {
Index: src/southbridge/via/vt8237r/vt8237r_ide.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_ide.c (revision 3542)
+++ src/southbridge/via/vt8237r/vt8237r_ide.c (working copy)
@@ -44,6 +44,7 @@
sb->ide1_enable ? "enabled" : "disabled");
enables = pci_read_config8(dev, IDE_CS) & ~0x3;
enables |= (sb->ide0_enable << 1) | sb->ide1_enable;
+// enables |= 3; /* XXX */
pci_write_config8(dev, IDE_CS, enables);
enables = pci_read_config8(dev, IDE_CS);
printk_debug("Enables in reg 0x40 read back as 0x%x\n", enables);
Index: src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- src/southbridge/via/vt8237r/vt8237r_lpc.c (revision 3542)
+++ src/southbridge/via/vt8237r/vt8237r_lpc.c (working copy)
@@ -247,7 +247,7 @@
/* FIXME: Map 4MB of flash into the address space,
* this should be in CAR call.
*/
- /* pci_write_config8(dev, 0x41, 0x7f); */
+ pci_write_config8(dev, 0x41, 0x7f);
/* Set bit 6 of 0x40 (I/O recovery time).
* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
@@ -272,7 +272,7 @@
pci_write_config8(dev, 0x59, 0x80);
/* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
- pci_write_config8(dev, 0x5B, 0xb);
+ pci_write_config8(dev, 0x5B, 0x9);
/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low). */
pci_write_config8(dev, 0x48, 0x8c);
Index: src/mainboard/via/epia-cn/Config.lb
===================================================================
--- src/mainboard/via/epia-cn/Config.lb (revision 3542)
+++ src/mainboard/via/epia-cn/Config.lb (working copy)
@@ -98,12 +98,14 @@
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
device pci f.0 on end # IDE
- register "fn_ctrl_lo" = "0x8a"
- register "fn_ctrl_hi" = "0x9d"
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.3 on end # USB 1.1
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
chip superio/via/vt1211 # Super I/O
device pnp 2e.0 off # Floppy
Index: src/mainboard/via/epia-cn/Options.lb
===================================================================
--- src/mainboard/via/epia-cn/Options.lb (revision 3542)
+++ src/mainboard/via/epia-cn/Options.lb (working copy)
@@ -94,7 +94,7 @@
default _RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
+default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
default HOSTCC = "gcc"
##
Index: src/mainboard/via/epia-cn/auto.c
===================================================================
--- src/mainboard/via/epia-cn/auto.c (revision 3542)
+++ src/mainboard/via/epia-cn/auto.c (working copy)
@@ -51,38 +51,17 @@
#include "northbridge/via/cn700/raminit.c"
-static void enable_mainboard_devices(void)
+static void enable_mainboard_devices(void)
{
device_t dev;
u8 reg;
-
- /*
- * If I enable SATA, FILO will not find the IDE disk, so I'll disable
- * SATA here. To not conflict with PCI spec, I'll move IDE device
- * from 00:0f.1 to 00:0f.0.
- */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT6420_SATA), 0);
- if (dev != PCI_DEV_INVALID) {
- /* Enable PATA. */
- reg = pci_read_config8(dev, 0xd1);
- reg |= 0x08;
- pci_write_config8(dev, 0xd1, reg);
- reg = pci_read_config8(dev, 0x49);
- reg |= 0x80;
- pci_write_config8(dev, 0x49, reg);
- } else {
- print_debug("No SATA device\r\n");
- }
-
- /* Disable SATA, and PATA device will be 00:0f.0. */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
- die("Southbridge not found!!!\r\n");
- reg = pci_read_config8(dev, 0x50);
- reg |= 0x08;
- pci_write_config8(dev, 0x50, reg);
+ die("Southbridge not found!!!\n");
+
+ pci_write_config8(dev, 0x50, 0x80);
+ pci_write_config8(dev, 0x51, 0x1d);
}
static const struct mem_controller ctrl = {
Index: src/northbridge/via/cn700/raminit.c
===================================================================
--- src/northbridge/via/cn700/raminit.c (revision 3542)
+++ src/northbridge/via/cn700/raminit.c (working copy)
@@ -366,7 +366,7 @@
/* dram duty control */
pci_write_config8(ctrl->d0f3, 0xed, 0x10);
- /* SMM and APIC deocoding, we donot use SMM */
+ /* SMM and APIC deocoding, we do not use SMM */
reg = 0x29;
pci_write_config8(ctrl->d0f3, 0x86, reg);
/* SMM and APIC decoding mirror */
Index: src/northbridge/via/cn700/vga.c
===================================================================
--- src/northbridge/via/cn700/vga.c (revision 3542)
+++ src/northbridge/via/cn700/vga.c (working copy)
@@ -47,11 +47,11 @@
print_debug("Copying BOCHS Bios to 0xf000\n");
/* Copy the BOCHs BIOS from 0xFFFFFFFF - ROM_SIZE - BOCHs size (64k) to 0xf0000
This is for compatibility with the VGA ROM's BIOS callbacks */
- memcpy(0xf0000, (0xFFFFFFFF - ROM_SIZE - 0x10000), 0x10000);
+ memcpy(0xf0000, (0xFFFFFFFF - ROM_SIZE - 0xffff), 0x10000);
printk_debug("Initializing VGA\n");
- pci_write_config8(dev, 0x3c, 0xb);
+// pci_write_config8(dev, 0x3c, 0xb);
/* Set memory rate to 200MHz */
outb(0x3d, CRTM_INDEX);
@@ -71,8 +71,8 @@
pci_write_config8(dev, 0x0d, 0x20);
pci_write_config32(dev,0x10, 0xf4000008);
pci_write_config32(dev,0x14, 0xfb000000);
- pci_write_config8(dev, 0x3e, 0x02);
- pci_write_config8(dev, 0x3c, 0x0a);
+// pci_write_config8(dev, 0x3e, 0x02);
+// pci_write_config8(dev, 0x3c, 0x0a);
printk_debug("INSTALL REAL-MODE IDT\n");
Index: targets/via/epia-cn/Config.lb
===================================================================
--- targets/via/epia-cn/Config.lb (revision 3542)
+++ targets/via/epia-cn/Config.lb (working copy)
@@ -22,15 +22,22 @@
target via_epia_cn
mainboard via/epia-cn
-#
-# Generate the final ROM like this:
-# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
-#
-option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+option MAXIMUM_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=8
+option CONFIG_CONSOLE_SERIAL8250=1
+## coreboot C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
+##
+## Generate the final ROM like this:
+## cat vgabios bochsbios coreboot.rom > coreboot.rom.final
+##
+#option ROM_SIZE = (512 * 1024) - (64 * 1024) - (64 * 1024)
+
romimage "image"
option COREBOOT_EXTRA_VERSION = "-epiacn"
- payload ../payload.elf
+ payload ../filo-0.5/filo.elf
end
buildrom ./coreboot.rom ROM_SIZE "image"
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