Author: stuge
Date: 2008-09-01 03:48:07 +0200 (Mon, 01 Sep 2008)
New Revision: 3556
Modified:
trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c
trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c
trunk/coreboot-v2/src/northbridge/via/cn700/vga.c
trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c
trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
trunk/coreboot-v2/targets/via/epia-cn/Config.lb
Log:
This patch gets the Epia-CN working without ACPI or APIC.
All devices work, no irq storms. Enjoy.
Signed-off-by: Bari Ari <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb 2008-08-31
22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Config.lb 2008-09-01
01:48:07 UTC (rev 3556)
@@ -98,12 +98,14 @@
register "ide0_80pin_cable" = "0"
register "ide1_80pin_cable" = "0"
device pci f.0 on end # IDE
- register "fn_ctrl_lo" = "0x8a"
- register "fn_ctrl_hi" = "0x9d"
- device pci 10.0 on end # USB 1.1
- device pci 10.1 on end # USB 1.1
- device pci 10.2 on end # USB 1.1
- device pci 10.3 on end # USB 1.1
+ register "fn_ctrl_lo" = "0x80"
+ register "fn_ctrl_hi" = "0x1d"
+ device pci 10.0 on end # OHCI
+ device pci 10.1 on end # OHCI
+ device pci 10.2 on end # OHCI
+ device pci 10.3 on end # OHCI
+ device pci 10.4 on end # EHCI
+ device pci 10.5 on end # UDCI
device pci 11.0 on # Southbridge LPC
chip superio/via/vt1211 # Super I/O
device pnp 2e.0 off # Floppy
Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2008-08-31
22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/Options.lb 2008-09-01
01:48:07 UTC (rev 3556)
@@ -94,7 +94,7 @@
default _RAMBASE = 0x00004000
default CONFIG_ROM_PAYLOAD = 1
default CROSS_COMPILE = ""
-default CC = "$(CROSS_COMPILE)gcc -m32"
+default CC = "$(CROSS_COMPILE)gcc -m32 -fno-stack-protector"
default HOSTCC = "gcc"
##
Modified: trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c 2008-08-31 22:10:35 UTC
(rev 3555)
+++ trunk/coreboot-v2/src/mainboard/via/epia-cn/auto.c 2008-09-01 01:48:07 UTC
(rev 3556)
@@ -55,34 +55,27 @@
{
device_t dev;
u8 reg;
+
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
+ if (dev == PCI_DEV_INVALID)
+ die("Southbridge not found!!!\n");
- /*
- * If I enable SATA, FILO will not find the IDE disk, so I'll disable
- * SATA here. To not conflict with PCI spec, I'll move IDE device
- * from 00:0f.1 to 00:0f.0.
+ /* bit=0 means enable function (per CX700 datasheet)
+ * 5 16.1 USB 2
+ * 4 16.0 USB 1
+ * 3 15.0 SATA and PATA
+ * 2 16.2 USB 3
+ * 1 16.4 USB EHCI
*/
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT6420_SATA), 0);
- if (dev != PCI_DEV_INVALID) {
- /* Enable PATA. */
- reg = pci_read_config8(dev, 0xd1);
- reg |= 0x08;
- pci_write_config8(dev, 0xd1, reg);
- reg = pci_read_config8(dev, 0x49);
- reg |= 0x80;
- pci_write_config8(dev, 0x49, reg);
- } else {
- print_debug("No SATA device\r\n");
- }
+ pci_write_config8(dev, 0x50, 0x80);
- /* Disable SATA, and PATA device will be 00:0f.0. */
- dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
- PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
- if (dev == PCI_DEV_INVALID)
- die("Southbridge not found!!!\r\n");
- reg = pci_read_config8(dev, 0x50);
- reg |= 0x08;
- pci_write_config8(dev, 0x50, reg);
+ /* bit=1 means enable internal function (per CX700 datasheet)
+ * 3 Internal RTC
+ * 2 Internal PS2 Mouse
+ * 1 Internal KBC Configuration
+ * 0 Internal Keyboard Controller
+ */
+ pci_write_config8(dev, 0x51, 0x1d);
}
static const struct mem_controller ctrl = {
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c 2008-08-31
22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/raminit.c 2008-09-01
01:48:07 UTC (rev 3556)
@@ -366,7 +366,7 @@
/* dram duty control */
pci_write_config8(ctrl->d0f3, 0xed, 0x10);
- /* SMM and APIC deocoding, we donot use SMM */
+ /* SMM and APIC decoding, we do not use SMM */
reg = 0x29;
pci_write_config8(ctrl->d0f3, 0x86, reg);
/* SMM and APIC decoding mirror */
Modified: trunk/coreboot-v2/src/northbridge/via/cn700/vga.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/via/cn700/vga.c 2008-08-31 22:10:35 UTC
(rev 3555)
+++ trunk/coreboot-v2/src/northbridge/via/cn700/vga.c 2008-09-01 01:48:07 UTC
(rev 3556)
@@ -45,14 +45,12 @@
u8 reg8;
print_debug("Copying BOCHS Bios to 0xf000\n");
-/* Copy the BOCHs BIOS from 0xFFFFFFFF - ROM_SIZE - BOCHs size (64k) to 0xf0000
- This is for compatibility with the VGA ROM's BIOS callbacks */
- memcpy(0xf0000, (0xFFFFFFFF - ROM_SIZE - 0x10000), 0x10000);
+ /* Copy BOCHS BIOS from 4G-ROM_SIZE-64k (in flash) to 0xf0000 (in RAM)
+ * This is for compatibility with the VGA ROM's BIOS callbacks */
+ memcpy(0xf0000, (0xffffffff - ROM_SIZE - 0xffff), 0x10000);
printk_debug("Initializing VGA\n");
- pci_write_config8(dev, 0x3c, 0xb);
-
/* Set memory rate to 200MHz */
outb(0x3d, CRTM_INDEX);
reg8 = inb(CRTM_DATA);
@@ -71,8 +69,6 @@
pci_write_config8(dev, 0x0d, 0x20);
pci_write_config32(dev,0x10, 0xf4000008);
pci_write_config32(dev,0x14, 0xfb000000);
- pci_write_config8(dev, 0x3e, 0x02);
- pci_write_config8(dev, 0x3c, 0x0a);
printk_debug("INSTALL REAL-MODE IDT\n");
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c 2008-08-31
22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r.c 2008-09-01
01:48:07 UTC (rev 3556)
@@ -79,8 +79,6 @@
pci_write_config8(dev, 0x51, sb->fn_ctrl_hi);
/* TODO: If SATA is disabled, move IDE to fn0 to conform PCI specs. */
- /* Extend ROM decode to 1MB FFC00000 - FFFFFFFF */
- pci_write_config8(dev, 0x41, 0x7f);
}
struct chip_operations southbridge_via_vt8237r_ops = {
Modified: trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2008-08-31
22:10:35 UTC (rev 3555)
+++ trunk/coreboot-v2/src/southbridge/via/vt8237r/vt8237r_lpc.c 2008-09-01
01:48:07 UTC (rev 3556)
@@ -244,10 +244,20 @@
enables |= 0x80;
pci_write_config8(dev, 0x6C, enables);
- /* FIXME: Map 4MB of flash into the address space,
- * this should be in CAR call.
+ /*
+ * ROM decode
+ * bit range
+ * 7 000E0000h-000EFFFFh
+ * 6 FFF00000h-FFF7FFFFh
+ * 5 FFE80000h-FFEFFFFFh
+ * 4 FFE00000h-FFE7FFFFh
+ * 3 FFD80000h-FFDFFFFFh
+ * 2 FFD00000h-FFD7FFFFh
+ * 1 FFC80000h-FFCFFFFFh
+ * 0 FFC00000h-FFC7FFFFh
+ * So 0x7f here sets ROM decode to FFC00000-FFFFFFFF or 4Mbyte.
*/
- /* pci_write_config8(dev, 0x41, 0x7f); */
+ pci_write_config8(dev, 0x41, 0x7f);
/* Set bit 6 of 0x40 (I/O recovery time).
* IMPORTANT FIX - EISA = ECLR reg at 0x4d0! Decoding must be on so
@@ -271,8 +281,14 @@
/* ROM memory cycles go to LPC. */
pci_write_config8(dev, 0x59, 0x80);
- /* Bypass APIC De-Assert Message, INTE#, INTF#, INTG#, INTH# as PCI. */
- pci_write_config8(dev, 0x5B, 0xb);
+ /*
+ * bit meaning
+ * 3 Bypass APIC De-Assert Message (1=Enable)
+ * 1 possibly "INTE#, INTF#, INTG#, INTH# as PCI"
+ * bit 1=1 works for Aaron at VIA, bit 1=0 works for jakllsch
+ * 0 Dynamic Clock Gating Main Switch (1=Enable)
+ */
+ pci_write_config8(dev, 0x5b, 0x9);
/* Set Read Pass Write Control Enable (force A2 from APIC FSB to low).
*/
pci_write_config8(dev, 0x48, 0x8c);
Modified: trunk/coreboot-v2/targets/via/epia-cn/Config.lb
===================================================================
--- trunk/coreboot-v2/targets/via/epia-cn/Config.lb 2008-08-31 22:10:35 UTC
(rev 3555)
+++ trunk/coreboot-v2/targets/via/epia-cn/Config.lb 2008-09-01 01:48:07 UTC
(rev 3556)
@@ -22,6 +22,13 @@
target via_epia_cn
mainboard via/epia-cn
+option MAXIMUM_CONSOLE_LOGLEVEL=8
+option DEFAULT_CONSOLE_LOGLEVEL=8
+option CONFIG_CONSOLE_SERIAL8250=1
+
+# coreboot C code runs at this location in RAM
+option _RAMBASE=0x00004000
+
#
# Generate the final ROM like this:
# cat vgabios bochsbios coreboot.rom > coreboot.rom.final
--
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