Carl-Daniel Hailfinger wrote:
Hi Marc,
I'm working on v3 and K8 setup. Right now, we try to determine whether
we rebooted because of INIT by looking at bit 11 of MTRRdefType because
it survives INIT and doesn't survive a cold or warm reboot. Although
this is a nice generic way, we can only read it early in stage0 asm
because we clobber it late in stage0 asm.
HyperTransport Initialization Control Register Function 0 Offset 6Ch Bit
6: InitDet looks exactly like what we want for that, and it is not
clobbered. Quoting from a really old BKDG (26094 Rev. 3.30 February 2006):
"INIT Detect (InitDet)—Bit 6. This bit may be used to distinguish
between an INIT and a warm/cold reset by setting the bit to 1 before an
initialization event is generated. This bit is cleared by a warm or cold
reset but not by an INIT."
Newer BKDGs say the same, so my question is how far back into the past
(in terms of CPUs supported by coreboot v2) and how far into the future
we can rely on this. It would certainly allow our stage0/stage1 code to
enjoy a cleaner design, not to mention improved readability.
Regards,
Carl-Daniel
Yes, 6Ch Bit 6: InitDet is a better way to do it. The 3.30 BKDG covers
rev a-e so it should be in all revisions of k8. It is also in the
Barcelona and I expect in all future versions. It looks like it is used
in K8 and Fam10 code. Grep for HTIC_INIT_Detect
Marc
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Marc Jones
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