-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Hello
Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the D1F0 bridge without activated I/O and MEM resources, otherwise it will hang whole PCI bus. U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why does we not. Second small change just changes a bit which controls the PSTATECTL logic. Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]> Rudolf -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFIwGJB3J9wPJqZRNURAipWAKCCs1kH0IDM5yVvQoIml/8Oztvk5wCdH+qk UvQL4Ma5GKl34JrlSjXF8xI= =zC2s -----END PGP SIGNATURE-----
Index: src/southbridge/via/k8t890/k8t890_bridge.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_bridge.c (revision 3565)
+++ src/southbridge/via/k8t890/k8t890_bridge.c (working copy)
@@ -24,8 +24,8 @@
static void bridge_enable(struct device *dev)
{
+ u8 tmp;
print_debug("B188 device dump\n");
-
/* VIA recommends this, sorry no known info. */
writeback(dev, 0x40, 0x91);
@@ -44,6 +44,12 @@
writeback(dev, 0x3e, 0x16);
dump_south(dev);
+
+ /* disable I/O and memory decode, or it freezes PCI bus during BAR sizing */
+ tmp = pci_read_config8(dev, PCI_COMMAND);
+ tmp &= ~0x3;
+ pci_write_config8(dev, PCI_COMMAND, tmp);
+
}
static const struct device_operations bridge_ops = {
Index: src/southbridge/via/k8t890/k8t890_host_ctrl.c
===================================================================
--- src/southbridge/via/k8t890/k8t890_host_ctrl.c (revision 3565)
+++ src/southbridge/via/k8t890/k8t890_host_ctrl.c (working copy)
@@ -105,8 +105,8 @@
/* Arbitration control */
pci_write_config8(dev, 0xa5, 0x3c);
- /* Arbitration control 2 */
- pci_write_config8(dev, 0xa6, 0x82);
+ /* Arbitration control 2, Enable C2NOW delay to PSTATECTL */
+ pci_write_config8(dev, 0xa6, 0x83);
}
k.patch.sig
Description: Binary data
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