2008/9/5 Stefan Reinauer <[EMAIL PROTECTED]> > Carl-Daniel Hailfinger wrote: > > On 05.09.2008 12:54, Stefan Reinauer wrote: > > > > > >> On 05.09.2008 09:45, Jackie Pan wrote: > >> > >>> if it's possible to place code into cache-emulated RAM > >>> > >> Core 2 Duo can do cache for ram and code... But it works well enough > >> to just set an mtrr to make rom cacheable during car and that also > >> works for older intel CPUs > >> > > > > We're talking about different things. > > Jackie was talking about executing code stored inside the pseudo-RAM CAR > > area. I was talking about that as well. > > Stefan wrote about using cache for code outside the CAR area. > > > No, not at all different things. As I said, the Core 2 Duo can execute > code stored in CAR. > > > > -- > coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. > Tel.: +49 761 7668825 • Fax: +49 761 7664613 > Email: [EMAIL PROTECTED] • http://www.coresystems.de/ > Registergericht: Amtsgericht Freiburg • HRB 7656 > Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 > > Hi Stefan, I'm very curious about how you achieve this. As Intel's separate L1 data cache and instruction cache,after checking the prog. manual I come to the conclusion that the i-cache can only be filled by instruction fetching process(or am i wrong?), when I copy code into the CAR region(i.e., not by caching of the XIP region using MTRR), the data I supplied goes directly into the d-cache, at the same time the corresponding line in the i-cache(if any) gets invalidated immediately, or more exactly for the CAR case, there's no such line in the i-cache at all because there's not been any instruction fetching targeting at the CAR region before. Thus it seems impossible to synchronize the i-cache and d-cache without a RAM as backup.
let me guess, are you implying storing to another core's cache while using MESI for the purpose of synchronizing?
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