On Wed, Sep 10, 2008 at 8:56 AM, Tim ter Laak <[EMAIL PROTECTED]> wrote: > Hello Mats and others, > > Like you, I am trying to get Coreboot-v2 up and running on a 440BX-based > board (Abit AB-BM6), with more than the currently hardcoded 64 MB of RAM. I > think I'm also running into the same problem. > > My current setup involves 384 MB of RAM, with the appropriate changes to the > hardcoded values in raminit.c (I haven't tried auto-detecting them yet, but > I'm curious for your patch), and uses Coreinfo as the payload for now. > > So long as I didn't change the values hardcoding the 64 MB limit, I could > boot fine into the payload, even with all three DIMMs present. With the > changes in raminit.c, elfboot/Coreinfo stops with an exception 6 (illegal > opcode), as per the log below. > > The curious thing is though, that when I first boot Linux with the original > BIOS, flash the chip to Coreboot, and then do a warm reboot into my freshly > burned Coreboot, it does succeed. Because of this, I'm guessing there's > something that Coreboot neglects to initialize, but luckily also doesn't > reset. > > I've compared the dumps from "Northbridge following SDRAM init:" for the > cold boot and the warm reboot from Linux, and there are indeed some > differences. My prime suspect for now is the Memory Buffer Strength Control > Register (0x69-0x6e), but I haven't had the chance to test that yet, and am > not certain by a long shot that it's it. I'm including the dumps below, in > case you can use them to better understand the problem > with your own board. > > With a bit of luck I can test my theory this evening, I'll keep you posted. > > Kind regards, > Tim.
Can you also include lspci -xxx -s 0:0.0 from the stock bios? Thanks, Corey -- coreboot mailing list [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
