OK, the new code properly sets parent links and also boots on both
simnow and dbe62.
I am attaching my statictree.c for perusal.
thanks
ron
#include <statictree.h>
struct device dev_root;
struct device dev_cpus;
struct device dev_apic_0;
struct device dev_domain_0_pci_1_0;
struct device dev_domain_0_pci0_18_0_pci_0_0;
struct device dev_domain_0_pci0_18_0_pci_4_0;
struct device dev_domain_0_pci0_18_0_pci_5_0;
struct device dev_domain_0_pci0_18_0;
struct device dev_domain_0_pci1_18_0;
struct device dev_domain_0_pci2_18_0_pci_2_0;
struct device dev_domain_0_pci2_18_0;
struct device dev_domain_0_ioport_2e;
struct device dev_domain_0;
const char *mainboard_vendor = "AMD";
const char *mainboard_name = "Serengeti";
struct device dev_root = {
.path = { .type = DEVICE_PATH_ROOT },
.link = {
[0] = {
.dev = &dev_root,
.link = 0,
.children = &dev_cpus
},
},
.links = 1,
.bus = &dev_root.link[0],
.next = &dev_cpus,
.ops = &default_dev_ops_root,
.dtsname = "root",
.enabled = 1
};
struct device dev_cpus = {
.sibling = &dev_apic_0,
.links = 0,
.bus = &dev_root.link[0],
.next = &dev_apic_0,
.dtsname = "cpus",
.enabled = 1
};
struct device dev_apic_0 = {
.path = {.type=DEVICE_PATH_APIC,{.apic={ 0x0 }}},
.sibling = &dev_domain_0,
.links = 0,
.bus = &dev_root.link[0],
.next = &dev_domain_0_pci_1_0,
.dtsname = "apic_0",
.enabled = 1
};
struct device dev_domain_0 = {
.path = {.type=DEVICE_PATH_PCI_DOMAIN,{.pci_domain={ .domain = 0x0 }}},
.link = {
[0] = {
.dev = &dev_domain_0,
.link = 0,
.children = &dev_domain_0_pci_1_0
},
},
.links = 1,
.bus = &dev_root.link[0],
.dtsname = "domain_0",
.enabled = 1
};
struct device dev_domain_0_pci_1_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x1, 0x0)}}},
.sibling = &dev_domain_0_pci0_18_0,
.links = 0,
.bus = &dev_domain_0.link[0],
.next = &dev_domain_0_pci0_18_0_pci_0_0,
.dtsname = "domain_0_pci_1_0",
.enabled = 1
};
struct northbridge_amd_k8_pci_config domain_0_pci0_18_0 = {
}; /*domain_0_pci0_18_0*/
struct device dev_domain_0_pci0_18_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18, 0x0)}}},
.device_configuration = &domain_0_pci0_18_0,
.ops = &k8_ops,
.sibling = &dev_domain_0_pci1_18_0,
.link = {
[0] = {
.dev = &dev_domain_0_pci0_18_0,
.link = 0,
.children = &dev_domain_0_pci0_18_0_pci_0_0
},
[1] = {
.dev = &dev_domain_0_pci1_18_0,
.link = 1,
},
[2] = {
.dev = &dev_domain_0_pci2_18_0,
.link = 2,
.children = &dev_domain_0_pci2_18_0_pci_2_0
},
},
.links = 3,
.bus = &dev_domain_0.link[0],
.next = &dev_domain_0_pci1_18_0,
.dtsname = "domain_0_pci0_18_0",
.enabled = 1
};
struct southbridge_amd_amd8111_amd8111_config domain_0_pci0_18_0_pci_0_0 = {
}; /*domain_0_pci0_18_0_pci_0_0*/
struct device dev_domain_0_pci0_18_0_pci_0_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x0, 0x0)}}},
.device_configuration = &domain_0_pci0_18_0_pci_0_0,
.ops = &amd8111,
.sibling = &dev_domain_0_pci0_18_0_pci_4_0,
.links = 0,
.bus = &dev_domain_0_pci0_18_0.link[0],
.next = &dev_domain_0_pci0_18_0_pci_4_0,
.dtsname = "domain_0_pci0_18_0_pci_0_0",
.enabled = 1
};
struct southbridge_amd_amd8111_ide_config domain_0_pci0_18_0_pci_4_0 = {
.ide0_enable = 0x0,
.ide1_enable = 0x1,
}; /*domain_0_pci0_18_0_pci_4_0*/
struct device dev_domain_0_pci0_18_0_pci_4_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x4, 0x0)}}},
.device_configuration = &domain_0_pci0_18_0_pci_4_0,
.ops = &amd8111_ide,
.sibling = &dev_domain_0_pci0_18_0_pci_5_0,
.links = 0,
.bus = &dev_domain_0_pci0_18_0.link[0],
.next = &dev_domain_0_pci0_18_0_pci_5_0,
.dtsname = "domain_0_pci0_18_0_pci_4_0",
.enabled = 1
};
struct southbridge_amd_amd8111_nic_config domain_0_pci0_18_0_pci_5_0 = {
.phy_lowreset = 0x0,
}; /*domain_0_pci0_18_0_pci_5_0*/
struct device dev_domain_0_pci0_18_0_pci_5_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x5, 0x0)}}},
.device_configuration = &domain_0_pci0_18_0_pci_5_0,
.ops = &amd8111_nic,
.links = 0,
.bus = &dev_domain_0_pci0_18_0.link[0],
.next = &dev_domain_0_pci0_18_0,
.dtsname = "domain_0_pci0_18_0_pci_5_0",
.enabled = 1
};
struct northbridge_amd_k8_pci_config domain_0_pci1_18_0 = {
}; /*domain_0_pci1_18_0*/
struct device dev_domain_0_pci1_18_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18, 0x0)}}},
.device_configuration = &domain_0_pci1_18_0,
.ops = &k8_ops,
.sibling = &dev_domain_0_pci2_18_0,
.links = 0,
.bus = &dev_domain_0_pci0_18_0.link[1],
.next = &dev_domain_0_pci2_18_0_pci_2_0,
.dtsname = "domain_0_pci1_18_0",
.enabled = 1
};
struct northbridge_amd_k8_pci_config domain_0_pci2_18_0 = {
}; /*domain_0_pci2_18_0*/
struct device dev_domain_0_pci2_18_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x18, 0x0)}}},
.device_configuration = &domain_0_pci2_18_0,
.ops = &k8_ops,
.sibling = &dev_domain_0_ioport_2e,
.links = 0,
.bus = &dev_domain_0_pci0_18_0.link[2],
.next = &dev_domain_0_ioport_2e,
.dtsname = "domain_0_pci2_18_0",
.enabled = 1
};
struct device dev_domain_0_pci2_18_0_pci_2_0 = {
.path = {.type=DEVICE_PATH_PCI,{.pci={ .devfn = PCI_DEVFN(0x2, 0x0)}}},
.links = 0,
.bus = &dev_domain_0_pci0_18_0.link[2],
.next = &dev_domain_0_pci2_18_0,
.dtsname = "domain_0_pci2_18_0_pci_2_0",
.enabled = 1
};
struct superio_winbond_w83627hf_dts_config domain_0_ioport_2e = {
.floppydev = 0x0,
.floppyenable = 0x0,
.floppyio = 0x3f0,
.floppyirq = 0x60,
.floppydrq = 0x2,
.ppdev = 0x2,
.ppenable = 0x0,
.ppio = 0x378,
.ppirq = 0x7,
.com1dev = 0x2,
.com1enable = 0x1,
.com1io = 0x3f8,
.com1irq = 0x4,
.com2dev = 0x3,
.com2enable = 0x0,
.com2io = 0x2f8,
.com2irq = 0x3,
.kbdev = 0x5,
.kbenable = 0x0,
.kbio = 0x60,
.kbio2 = 0x62,
.kbirq = 0x1,
.kbirq2 = 0xc,
.cirdev = 0x6,
.cirenable = 0x0,
.gamedev = 0x7,
.gameenable = 0x0,
.gameio = 0x220,
.gameio2 = 0x400,
.gameirq = 0x9,
.gpio2dev = 0x8,
.gpio2enable = 0x0,
.gpio3dev = 0x9,
.gpio3enable = 0x0,
.acpidev = 0xa,
.acpienable = 0x0,
.hwmdev = 0xb,
.hwmenable = 0x0,
.hwmio = 0x290,
.hwmirq = 0x5,
}; /*domain_0_ioport_2e*/
struct device dev_domain_0_ioport_2e = {
.path = {.type=DEVICE_PATH_IOPORT,{.ioport={.iobase=0x2e}}},
.device_configuration = &domain_0_ioport_2e,
.links = 0,
.bus = &dev_domain_0.link[0],
.next = &dev_domain_0,
.dtsname = "domain_0_ioport_2e",
.enabled = 1
};
struct device_operations *all_device_operations[] = {
&k8_ops,
&amd8111,
&amd8111_ide,
&amd8111_nic,
&k8_ops,
&k8_ops,
0
};
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
