Author: mjones
Date: 2008-09-19 22:16:25 +0200 (Fri, 19 Sep 2008)
New Revision: 3585
Added:
trunk/coreboot-v2/src/cpu/amd/socket_S1G1/
trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
trunk/coreboot-v2/src/cpu/amd/socket_S1G1/chip.h
trunk/coreboot-v2/src/cpu/amd/socket_S1G1/socket_S1G1.c
Modified:
trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c
Log:
Add AMD K8 S1G1 socket support.
Signed-off-by: Michael Xie [EMAIL PROTECTED]
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Added: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb
(rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/Config.lb 2008-09-19 20:16:25 UTC
(rev 3585)
@@ -0,0 +1,19 @@
+uses CONFIG_CHIP_NAME
+uses K8_REV_F_SUPPORT
+uses K8_HT_FREQ_1G_SUPPORT
+uses DIMM_SUPPORT
+uses CPU_SOCKET_TYPE
+
+if CONFIG_CHIP_NAME
+ config chip.h
+end
+
+default K8_REV_F_SUPPORT=1
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+default DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1
+default CPU_SOCKET_TYPE=0x12
+
+object socket_S1G1.o
+
+dir /cpu/amd/model_fxx
Added: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/chip.h
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/chip.h
(rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/chip.h 2008-09-19 20:16:25 UTC
(rev 3585)
@@ -0,0 +1,4 @@
+extern struct chip_operations cpu_amd_socket_S1G1_ops;
+
+struct cpu_amd_socket_S1G1_config {
+};
Added: trunk/coreboot-v2/src/cpu/amd/socket_S1G1/socket_S1G1.c
===================================================================
--- trunk/coreboot-v2/src/cpu/amd/socket_S1G1/socket_S1G1.c
(rev 0)
+++ trunk/coreboot-v2/src/cpu/amd/socket_S1G1/socket_S1G1.c 2008-09-19
20:16:25 UTC (rev 3585)
@@ -0,0 +1,6 @@
+#include <device/device.h>
+#include "chip.h"
+
+struct chip_operations cpu_amd_socket_S1G1_ops = {
+ CHIP_NAME("Socket S1G1 CPU")
+};
Modified: trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c
===================================================================
--- trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2008-09-18
16:27:00 UTC (rev 3584)
+++ trunk/coreboot-v2/src/northbridge/amd/amdk8/raminit_f.c 2008-09-19
20:16:25 UTC (rev 3585)
@@ -1,8 +1,23 @@
-/* This should be done by Eric
- 2004.11 yhlu add 4 rank DIMM support
- 2004.12 yhlu add D0 support
- 2005.02 yhlu add E0 memory hole support
- 2005.10 yhlu make it support DDR2 only
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2002 Linux Networx
+ * (Written by Eric Biederman <[EMAIL PROTECTED]> for Linux Networx)
+ * Copyright (C) 2004 YingHai Lu
+ * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <cpu/x86/mem.h>
@@ -819,10 +834,10 @@
uint32_t ClkDis0;
#if CPU_SOCKET_TYPE == 0x10 /* L1 */
ClkDis0 = DTL_MemClkDis0;
-#else
- #if CPU_SOCKET_TYPE == 0x11 /* AM2 */
+#elif CPU_SOCKET_TYPE == 0x11 /* AM2 */
ClkDis0 = DTL_MemClkDis0_AM2;
- #endif
+#elif CPU_SOCKET_TYPE == 0x12 /* S1G1 */
+ ClkDis0 = DTL_MemClkDis0_S1g1;
#endif
dword = pci_read_config32(ctrl->f2, DRAM_TIMING_LOW); //Channel
A
@@ -2053,10 +2068,16 @@
}
}
- dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
- dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
- dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
- pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
+
+
+#if DIMM_SUPPORT == 0x0204
+ odt = 0x2; /* 150 ohms */
+#endif
+
+ dcl = pci_read_config32(ctrl->f2, DRAM_CONFIG_LOW);
+ dcl &= ~(DCL_DramTerm_MASK<<DCL_DramTerm_SHIFT);
+ dcl |= (odt & DCL_DramTerm_MASK) << (DCL_DramTerm_SHIFT);
+ pci_write_config32(ctrl->f2, DRAM_CONFIG_LOW, dcl);
}
@@ -2237,6 +2258,46 @@
#endif
+#if DIMM_SUPPORT==0x0204 /* DDR2 and SO-DIMM, S1G1 */
+ dword = 0x00111222;
+ dwordx = 0x002F2F00;
+
+ switch (meminfo->memclk_set) {
+ case DCH_MemClkFreq_200MHz: /* nothing to be set here */
+ break;
+ case DCH_MemClkFreq_266MHz:
+ if ((meminfo->single_rank_mask == 0)
+ && (meminfo->x4_mask == 0) && (meminfo->x16_mask))
+ dwordx = 0x002C2C00; /* Double rank x8 */
+ /* else SRx16, SRx8, DRx16 == 0x002F2F00 */
+ break;
+ case DCH_MemClkFreq_333MHz:
+ if ((meminfo->single_rank_mask == 1)
+ && (meminfo->x16_mask == 1)) /* SR x16 */
+ dwordx = 0x00272700;
+ else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
+ && (meminfo->single_rank_mask == 0)) { /* DR x8 */
+ SlowAccessMode = 1;
+ dwordx = 0x00002800;
+ } else { /* SR x8, DR x16 */
+ dwordx = 0x002A2A00;
+ }
+ break;
+ case DCH_MemClkFreq_400MHz:
+ if ((meminfo->single_rank_mask == 1)
+ && (meminfo->x16_mask == 1)) /* SR x16 */
+ dwordx = 0x00292900;
+ else if ((meminfo->x4_mask == 0) && (meminfo->x16_mask == 0)
+ && (meminfo->single_rank_mask == 0)) { /* DR x8 */
+ SlowAccessMode = 1;
+ dwordx = 0x00002A00;
+ } else { /* SR x8, DR x16 */
+ dwordx = 0x002A2A00;
+ }
+ break;
+ }
+#endif
+
#if DIMM_SUPPORT==0x0004 /* DDR2 and unbuffered */
/* for UNBUF DIMM */
dword = 0x00111222;
--
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