support for node id and core id. We've been faking this for two years now. Add functions to geode and k8 to support getting node id/core id. Everything is going multicore, which means everything will be smp, so I really am not too worried that we have a few empty functions -- cost is the one byte ret and the 5 byte call and the very rare usage of them both. Remove the empy stop_ap() function from stage1 and put it where it belongs -- in architecture code. Put the node_id_code_id struct in the generic cpu.h reorder includes. This compiles on k8 and AMP. Not tested, waiting for your comments. I'm not wedded to this idea but we need to do SOMETHING in stage1 -- there are two bits of code in there that depend on our knowing what node and core we are running on! Signed-off-by: Ronald G. Minnich Index: include/arch/x86/amd/k8/k8.h =================================================================== --- include/arch/x86/amd/k8/k8.h (revision 868) +++ include/arch/x86/amd/k8/k8.h (working copy) @@ -639,16 +639,6 @@ /* dual core support */ unsigned int read_nb_cfg_54(void); -struct node_core_id { - unsigned nodeid; - unsigned coreid; -}; - -/* use this to get the nodeid and core id of the current cpu - * (but not other CPUs) - */ -struct node_core_id get_node_core_id(void); - struct device; unsigned get_apicid_base(unsigned ioapic_num); void amd_sibling_init(struct device *cpu); Index: include/arch/x86/cpu.h =================================================================== --- include/arch/x86/cpu.h (revision 868) +++ include/arch/x86/cpu.h (working copy) @@ -82,12 +82,28 @@ u8 x86_mask; }; +/* core and node id. This was special to k8 in v2 but is in fact quite generic */ +struct node_core_id { + unsigned nodeid; + unsigned coreid; +}; + +/* use this to get the nodeid and core id of the current cpu + * (but not other CPUs). We're going to make this supported on all CPUs. + * multicore is used everywhere now. For single socket/single core CPUs they can + * just return a struct with 0s. This will simplify the stage1 code. + */ +struct node_core_id get_node_core_id(void); + /* prototypes for functions that may or may not be compiled in depending on cpu type */ void set_var_mtrr_x( unsigned long reg, u32 base_lo, u32 base_hi, u32 size_lo, u32 size_hi, unsigned long type); void set_var_mtrr( unsigned long reg, unsigned long base, unsigned long size, unsigned long type); +/* generic SMP functions required to be supported (even by non-SMP) + */ +void stop_ap(void); /** * Generic CPUID function. Index: mainboard/amd/serengeti/initram.c =================================================================== --- mainboard/amd/serengeti/initram.c (revision 869) +++ mainboard/amd/serengeti/initram.c (working copy) @@ -26,13 +26,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include Index: mainboard/amd/serengeti/Makefile =================================================================== --- mainboard/amd/serengeti/Makefile (revision 868) +++ mainboard/amd/serengeti/Makefile (working copy) @@ -27,6 +27,8 @@ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ $(src)/southbridge/amd/amd8111/stage1_ctrl.c \ $(src)/southbridge/amd/amd8111/stage1_enable_rom.c \ + $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/northbridge/amd/k8/coherent_ht.c \ $(src)/northbridge/amd/k8/libstage1.c \ @@ -38,10 +40,9 @@ $(src)/arch/x86/pci_ops_conf1.c \ $(src)/arch/x86/stage1_mtrr.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ - $(src)/arch/x86/amd/model_fxx/init_cpus.c \ $(src)/arch/x86/amd/model_fxx/dualcore.c \ - $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ $(src)/arch/x86/amd/model_fxx/fidvid.c \ + $(src)/arch/x86/amd/model_fxx/init_cpus.c \ $(src)/lib/clog2.c Index: arch/x86/geodelx/stage1.c =================================================================== --- arch/x86/geodelx/stage1.c (revision 867) +++ arch/x86/geodelx/stage1.c (working copy) @@ -20,6 +20,7 @@ #include #include +#include #include #include #include @@ -48,6 +49,27 @@ } /** + * Return core id/node id info. Always 0. + */ +struct node_core_id get_node_core_id(void) +{ + struct node_core_id id; + id.nodeid = 0; + id.coreid = 0; +} + +/** + * stop_ap. Hey, maybe someday we get multicore geodes. + * dont' get upset about this code -- the cost is a one byte ret. + */ +void stop_ap(void) +{ + // nothing yet if ever + post_code(POST_STAGE1_STOP_AP); +} + + +/** * Disable Cache As RAM (CAR) after memory is setup. * * Geode can write back the cache contents to RAM and continue on. Index: arch/x86/amd/model_fxx/dualcore.c =================================================================== --- arch/x86/amd/model_fxx/dualcore.c (revision 867) +++ arch/x86/amd/model_fxx/dualcore.c (working copy) @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -9,7 +10,6 @@ #include #include #include -#include #include #include #include Index: arch/x86/amd/model_fxx/stage1.c =================================================================== --- arch/x86/amd/model_fxx/stage1.c (revision 0) +++ arch/x86/amd/model_fxx/stage1.c (revision 0) @@ -0,0 +1,58 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2005 Advanced Micro Devices, Inc. + * Copyright (C) 2007 Stefan Reinauer + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * Stop all APs + * @param bsp_apicid The BSP apic id, to make sure we don't send ourselves the stop + */ +void allow_all_aps_stop(unsigned bsp_apicid) +{ + lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44); // allow aps to stop +} + +/** + * stop_ap. Called from stage1. + */ +void stop_ap(void) +{ + /* well, at time this is called, bsp_apicid *is* zero. It might change later. + * we need to figure this out. I don't know how. Global variable? + */ + allow_all_aps_stop(0); + post_code(POST_STAGE1_STOP_AP); +} + Index: arch/x86/amd/model_fxx/fidvid.c =================================================================== --- arch/x86/amd/model_fxx/fidvid.c (revision 867) +++ arch/x86/amd/model_fxx/fidvid.c (working copy) @@ -1,6 +1,7 @@ #include #include #include +#include #include #include #include @@ -8,7 +9,6 @@ #include #include #include -#include #include #include #include Index: arch/x86/amd/model_fxx/dualcore_id.c =================================================================== --- arch/x86/amd/model_fxx/dualcore_id.c (revision 867) +++ arch/x86/amd/model_fxx/dualcore_id.c (working copy) @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include Index: arch/x86/amd/model_fxx/init_cpus.c =================================================================== --- arch/x86/amd/model_fxx/init_cpus.c (revision 868) +++ arch/x86/amd/model_fxx/init_cpus.c (working copy) @@ -23,13 +23,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include #include @@ -288,15 +288,6 @@ printk(BIOS_DEBUG, "\r\n"); } -/** - * Stop all APs - * @param bsp_apicid The BSP apic id, to make sure we don't send ourselves the stop - */ -void allow_all_aps_stop(unsigned bsp_apicid) -{ - lapic_write(LAPIC_MSG_REG, (bsp_apicid << 24) | 0x44); // allow aps to stop -} - void STOP_CAR_AND_CPU(void) { disable_cache_as_ram(); // inline Index: arch/x86/stage1.c =================================================================== --- arch/x86/stage1.c (revision 867) +++ arch/x86/stage1.c (working copy) @@ -21,6 +21,7 @@ #include #include #include +#include #include #include #include @@ -43,12 +44,6 @@ void disable_car(void); void mainboard_pre_payload(void); -static void stop_ap(void) -{ - // nothing yet - post_code(POST_STAGE1_STOP_AP); -} - static void enable_rom(void) { // nothing here yet @@ -156,6 +151,7 @@ int ret; struct mem_file archive; void *entry; + struct node_core_id me; #ifdef CONFIG_PAYLOAD_ELF_LOADER struct mem_file result; int elfboot_mem(struct lb_memory *mem, void *where, int size); @@ -174,19 +170,21 @@ post_code(POST_STAGE1_MAIN); - // before we do anything, we want to stop if we dont run - // on the bootstrap processor. -#warning We do not want to check BIST here, we want to check whether we are BSC! - if (bist==0) { - // stop secondaries - stop_ap(); - } + me = get_node_core_id(); + /* before we do anything, we want to stop if we dont run + * on the bootstrap processor. + * stop_ap is responsible for NOT stopping the BSP + */ + stop_ap(); + /* Initialize global variables before we can think of using them. * NEVER run this on an AP! */ - global_vars_init(&globvars); - globvars.init_detected = init_detected; + if (me.nodeid == 0) { + global_vars_init(&globvars); + globvars.init_detected = init_detected; + } hardware_stage1(); Index: arch/x86/stage1_mtrr.c =================================================================== --- arch/x86/stage1_mtrr.c (revision 867) +++ arch/x86/stage1_mtrr.c (working copy) @@ -4,13 +4,13 @@ #include #include #include +#include #include #include #include #include #include #include -#include #include #include