Dear coreboot readers! This is the automated build check service of coreboot.
The developer "ruik" checked in revision 3587 to the coreboot source repository and caused the following changes: Change Log: Attached patch fixes at least one issue ;) During the PCI BAR sizing must be the D1F0 bridge without activated I/O and MEM resources, otherwise it will hang whole PCI bus. U-boot is also disabling the IO/MEM decode when sizing the BARs, dont know why does we not. Second small change just changes a bit which controls the PSTATECTL logic. Third change deals with the integrated VGA, which needs to be enabled early, so the VGA_EN is set along the bridges, and PCI K8 resource maps are set correctly. Finally the CPU accessible framebuffer is now disabled as it is not needed. Signed-off-by: Rudolf Marek <[EMAIL PROTECTED]> Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]> Build Log: Compilation of jetway:j7f24 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3587&device=j7f24&vendor=jetway Compilation of via:epia-cn is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=3587&device=epia-cn&vendor=via If something broke during this checkin please be a pain in ruik's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
