Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
On Mon, Sep 29, 2008 at 3:48 PM, Marc Jones <[EMAIL PROTECTED]> wrote: > This fixes the four platforms that the recent K8 changes broke. > Thanks, > Marc > > -- > Marc Jones > Senior Firmware Engineer > (970) 226-9684 Office > mailto:[EMAIL PROTECTED] > http://www.amd.com/embeddedprocessors > > AMD K8 platforms must use CAR so it makes sense to use the PRINK_IN_CAR > option. > This patch converts the following patches to use PRTINK_IN_CAR > amd/serngeti_cheetah > msi/ms9185 > msi/ms9828 > supermicro/h8dmr > > Signed-off-by: Marc Jones <[EMAIL PROTECTED]> > > Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb > =================================================================== > --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/Options.lb > 2008-09-29 16:05:06.000000000 -0600 > +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/Options.lb 2008-09-29 > 15:07:22.000000000 -0600 > @@ -286,7 +286,7 @@ > ## > ## The Serial Console > ## > -default CONFIG_USE_PRINTK_IN_CAR=0 > +default CONFIG_USE_PRINTK_IN_CAR=1 > > # To Enable the Serial Console > default CONFIG_CONSOLE_SERIAL8250=1 > Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c > =================================================================== > --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c > 2008-09-29 16:09:17.000000000 -0600 > +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c > 2008-09-29 15:15:47.000000000 -0600 > @@ -33,6 +33,7 @@ > #include "option_table.h" > #include "pc80/mc146818rtc_early.c" > > + > #if 0 > static void post_code(uint8_t value) { > #if 1 > @@ -64,11 +65,6 @@ > > #if CONFIG_USE_INIT == 0 > #include "lib/memcpy.c" > - #if CONFIG_USE_PRINTK_IN_CAR == 1 > - #include "lib/uart8250.c" > - #include "console/vtxprintf.c" > - #include "arch/i386/lib/printk_init.c" > - #endif > #endif > #include "northbridge/amd/amdk8/debug.c" > #include "cpu/amd/mtrr/amd_earlymtrr.c" > Index: coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c > =================================================================== > --- coreboot-v2.orig/src/mainboard/amd/serengeti_cheetah/apc_auto.c > 2008-09-29 16:17:07.000000000 -0600 > +++ coreboot-v2/src/mainboard/amd/serengeti_cheetah/apc_auto.c 2008-09-29 > 15:16:43.000000000 -0600 > @@ -24,11 +24,6 @@ > > #if CONFIG_USE_INIT == 0 > #include "lib/memcpy.c" > - #if CONFIG_USE_PRINTK_IN_CAR == 1 > - #include "lib/uart8250.c" > - #include "console/vtxprintf.c" > - #include "arch/i386/lib/printk_init.c" > - #endif > #endif > > #include "arch/i386/lib/console.c" > Index: coreboot-v2/src/mainboard/msi/ms9185/Options.lb > =================================================================== > --- coreboot-v2.orig/src/mainboard/msi/ms9185/Options.lb 2008-09-29 > 16:18:48.000000000 -0600 > +++ coreboot-v2/src/mainboard/msi/ms9185/Options.lb 2008-09-29 > 15:21:44.000000000 -0600 > @@ -104,7 +104,7 @@ > uses CONFIG_PCI_64BIT_PREF_MEM > > uses CONFIG_LB_MEM_TOPK > - > +uses CONFIG_USE_PRINTK_IN_CAR > > ### > ### Build options > @@ -222,7 +222,7 @@ > default DCACHE_RAM_BASE=0xcc000 > default DCACHE_RAM_SIZE=0x04000 > default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 > -default CONFIG_USE_INIT=0 > +default CONFIG_USE_INIT=0 > > ## > ## Build code to setup a generic IOAPIC > @@ -287,6 +287,7 @@ > ## > ## The Serial Console > ## > +default CONFIG_USE_PRINTK_IN_CAR=1 > > # To Enable the Serial Console > default CONFIG_CONSOLE_SERIAL8250=1 > Index: coreboot-v2/src/mainboard/msi/ms9282/Options.lb > =================================================================== > --- coreboot-v2.orig/src/mainboard/msi/ms9282/Options.lb 2008-09-29 > 16:28:46.000000000 -0600 > +++ coreboot-v2/src/mainboard/msi/ms9282/Options.lb 2008-09-29 > 15:22:01.000000000 -0600 > @@ -100,6 +100,7 @@ > uses CONFIG_COMPRESSED_PAYLOAD_LZMA > uses CONFIG_COMPRESSED_PAYLOAD_NRV2B > uses CONFIG_PRECOMPRESSED_PAYLOAD > +uses CONFIG_USE_PRINTK_IN_CAR > > ## ROM_SIZE is the size of boot ROM that this board will use. > #512K bytes > @@ -203,7 +204,6 @@ > default APIC_ID_OFFSET=0x10 > default LIFT_BSP_APIC_ID=0 > > - > ## > ## Build code to setup a generic IOAPIC > ## > @@ -267,7 +267,8 @@ > ## > ## The Serial Console > ## > - > +default CONFIG_USE_PRINTK_IN_CAR=1 > + > # To Enable the Serial Console > default CONFIG_CONSOLE_SERIAL8250=1 > > Index: coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb > =================================================================== > --- coreboot-v2.orig/src/mainboard/supermicro/h8dmr/Options.lb 2008-09-29 > 16:35:16.000000000 -0600 > +++ coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2008-09-29 > 15:21:14.000000000 -0600 > @@ -236,7 +236,7 @@ > default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000 > default CONFIG_USE_INIT=0 > > -default CONFIG_AP_CODE_IN_CAR=0 > +default CONFIG_AP_CODE_IN_CAR=1 > default MEM_TRAIN_SEQ=1 > default WAIT_BEFORE_CPUS_INIT=1 > > @@ -305,7 +305,7 @@ > ## > ## The Serial Console > ## > -default CONFIG_USE_PRINTK_IN_CAR=0 > +default CONFIG_USE_PRINTK_IN_CAR=1 > > # To Enable the Serial Console > default CONFIG_CONSOLE_SERIAL8250=1 > Index: coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb > =================================================================== > --- coreboot-v2.orig/targets/supermicro/h8dmr/Config-abuild.lb 2008-09-29 > 16:39:33.000000000 -0600 > +++ coreboot-v2/targets/supermicro/h8dmr/Config-abuild.lb 2008-09-29 > 15:39:57.000000000 -0600 > @@ -12,7 +12,7 @@ > romimage "normal" > option USE_FAILOVER_IMAGE=0 > option USE_FALLBACK_IMAGE=0 > - option ROM_IMAGE_SIZE=0x18000 > + option ROM_IMAGE_SIZE=0x20000 > option COREBOOT_EXTRA_VERSION=".0-normal" > payload __PAYLOAD__ > end > @@ -20,7 +20,7 @@ > romimage "fallback" > option USE_FAILOVER_IMAGE=0 > option USE_FALLBACK_IMAGE=1 > - option ROM_IMAGE_SIZE=0x18000 > + option ROM_IMAGE_SIZE=0x20000 > option COREBOOT_EXTRA_VERSION=".0-fallback" > payload __PAYLOAD__ > end > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot > -- coreboot mailing list: [email protected] http://www.coreboot.org/mailman/listinfo/coreboot
