Author: rminnich
Date: 2008-10-01 09:23:05 +0200 (Wed, 01 Oct 2008)
New Revision: 877
Modified:
coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
coreboot-v3/northbridge/amd/k8/dqs.c
coreboot-v3/northbridge/amd/k8/raminit.c
coreboot-v3/southbridge/nvidia/mcp55/ide.c
coreboot-v3/southbridge/nvidia/mcp55/lpc.c
coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
coreboot-v3/southbridge/nvidia/mcp55/pci.c
coreboot-v3/southbridge/nvidia/mcp55/pcie.c
coreboot-v3/southbridge/nvidia/mcp55/sata.c
coreboot-v3/southbridge/nvidia/mcp55/usb2.c
Log:
m57sli mostly builds again. The stage0 is too large at 24k.
We need to figure out if we should just grow stage0. My inclination is
to say 'yes'.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c
===================================================================
--- coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-10-01 06:47:51 UTC
(rev 876)
+++ coreboot-v3/arch/x86/amd/model_fxx/init_cpus.c 2008-10-01 07:23:05 UTC
(rev 877)
@@ -300,9 +300,9 @@
#if MEM_TRAIN_SEQ == 1
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid,
+void train_ram_on_node(unsigned nodeid, unsigned coreid,
struct sys_info *sysinfo,
- unsigned retcall);
+ void * retcall);
#endif
/**
@@ -479,7 +479,7 @@
/* this is not done on Serengeti. */
#if MEM_TRAIN_SEQ == 1
train_ram_on_node(id.nodeid, id.coreid, sysinfo,
- STOP_CAR_AND_CPU);
+ (void *)STOP_CAR_AND_CPU);
#endif
/* this is inline and there is no return. */
STOP_CAR_AND_CPU();
Modified: coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-01 06:47:51 UTC
(rev 876)
+++ coreboot-v3/mainboard/gigabyte/m57sli/mainboard.h 2008-10-01 07:23:05 UTC
(rev 877)
@@ -43,3 +43,6 @@
/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */
/* preferably by asking the CPU, not be a DEFINE! */
#define CPU_ADDR_BITS 40
+
+/* you don't want to set this in Kconfig or dts either. It's dangerous! */
+#define CONFIG_AP_CODE_IN_CAR 0
Modified: coreboot-v3/northbridge/amd/k8/dqs.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/dqs.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/northbridge/amd/k8/dqs.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -26,6 +26,7 @@
#include <macros.h>
#include <spd.h>
#include <cpu.h>
+#include <globalvars.h>
#include <msr.h>
#include <device/pci.h>
#include <pci_ops.h>
@@ -1938,10 +1939,11 @@
#if MEM_TRAIN_SEQ > 0
-static void dqs_timing(int i, const struct mem_controller *ctrl, struct
sys_info *sysinfo, unsigned int v)
+void dqs_timing(int i, const struct mem_controller *ctrl, struct sys_info
*sysinfo)
{
int ii;
+ int v = 1; /* used to be a parameter; consider making it one again */
u64 tsc[4];
@@ -1972,9 +1974,8 @@
}
tsc[1] = cycles();
if (DQS_TRAIN_DEBUG) {
- printk(BIOS_DEBUG, "set DQS timing:DQSPos: ");
+ printk(BIOS_DEBUG, "set DQS timing:DQSPos: %02x", i);
}
- print_debug_hex8(i);
}
if(train_DqsPos(ctrl, sysinfo)) {
@@ -1987,9 +1988,8 @@
tsc[2] = cycles();
if (DQS_TRAIN_DEBUG) {
- printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: ");
+ printk(BIOS_DEBUG, "set DQS timing:RcvrEn:Pass2: %02x\n", i);
}
- print_debug_hex8(i);
}
if(train_DqsRcvrEn(ctrl, 2, sysinfo)){
sysinfo->mem_trained[i]=0x83; //
@@ -2011,7 +2011,7 @@
if(v) {
for(ii=0;ii<4;ii++) {
- print_debug_dqs_tsc_x("Total DQS Training : tsc ", ii,
tsc[ii].hi, tsc[ii].lo);
+ printk(BIOS_ERR, "Total DQS Training : tsc %d: %llx", ii,
tsc[ii]);
}
}
@@ -2025,17 +2025,21 @@
#if MEM_TRAIN_SEQ == 1
static void train_ram(unsigned nodeid, struct sys_info *sysinfo, struct
sys_info *sysinfox)
{
- dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo, 0); // keep the
output tidy
+ dqs_timing(nodeid, &sysinfo->ctrl[nodeid], sysinfo); // keep the output
tidy
// memcpy(&sysinfox->dqs_rcvr_dly_a[nodeid * 2 *
8],&sysinfo->dqs_rcvr_dly_a[nodeid * 2 * 8], 2*8);
// memcpy(&sysinfox->dqs_delay_a[nodeid * 2 * 2 * 9],
&sysinfo->dqs_delay_a[nodeid * 2 * 2 * 9], 2 * 2 * 9);
sysinfox->mem_trained[nodeid] = sysinfo->mem_trained[nodeid];
}
static void copy_and_run_ap_code_in_car(unsigned ret_addr);
-static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct
sys_info *sysinfo, unsigned retcall)
+void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info
*sysinfo, void * retcall)
{
if(coreid) return; // only do it on core0
- struct sys_info *sysinfox = ((CONFIG_LB_MEM_TOPK<<10) -
DCACHE_RAM_GLOBAL_VAR_SIZE);
+ /* this is a little weird. We're going to get the address of the global
vars. But we're in CAR, so
+ * it's really private. We're going to copy from global memory, which
is node 0 memory, which
+ * is working at this point.
+ */
+ struct sys_info *sysinfox = & global_vars()->sys_info;
wait_till_sysinfo_in_ram(); // use pci to get it
if(sysinfox->mem_trained[nodeid] == 0x80) {
@@ -2046,7 +2050,7 @@
sysinfo->mem_trained[nodeid] = sysinfox->mem_trained[nodeid];
memcpy(&sysinfo->ctrl[nodeid], &sysinfox->ctrl[nodeid],
sizeof(struct mem_controller));
#else
- memcpy(sysinfo, sysinfox, DCACHE_RAM_GLOBAL_VAR_SIZE);
+ memcpy(sysinfo, sysinfox, sizeof(*sysinfo));
#endif
set_top_mem_ap(sysinfo->tom_k, sysinfo->tom2_k); // keep the
ap's tom consistent with bsp's
#if CONFIG_AP_CODE_IN_CAR == 0
@@ -2056,7 +2060,9 @@
#else
/* Can copy dqs_timing to ap cache and run from cache?
* we need coreboot_ap_car.rom? and treat it as coreboot_ram.rom
for ap ?
+ * not sure how we'll return.
*/
+#warning resolve issues about returning from the copy_and_run_ap_code_in_car.
copy_and_run_ap_code_in_car(retcall);
// will go back by jump
#endif
Modified: coreboot-v3/northbridge/amd/k8/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/k8/raminit.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/northbridge/amd/k8/raminit.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -2653,10 +2653,10 @@
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the hole_startk is valid, if it is equal
to basek, we need to decrease it some
- u32 basek_pri;
+ u32 basek_pri = 0;
for(i=0; i<controllers; i++) {
u32 base;
- unsigned base_k;
+ u32 base_k;
base = pci_conf1_read_config32(ctrl[0].f1, 0x40 + (i
<< 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
Modified: coreboot-v3/southbridge/nvidia/mcp55/ide.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/southbridge/nvidia/mcp55/ide.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -41,7 +41,7 @@
u16 word;
u8 byte;
- word = pci_conf1_read_config16(dev, 0x50);
+ word = pci_read_config16(dev, 0x50);
/* Ensure prefetch is disabled */
word &= ~((1 << 15) | (1 << 13));
if (conf->ide1_enable) {
@@ -56,15 +56,15 @@
word |= (1<<12);
word |= (1<<14);
- pci_conf1_write_config16(dev, 0x50, word);
+ pci_write_config16(dev, 0x50, word);
byte = 0x20 ; // Latency: 64-->32
- pci_conf1_write_config8(dev, 0xd, byte);
+ pci_write_config8(dev, 0xd, byte);
- dword = pci_conf1_read_config32(dev, 0xf8);
+ dword = pci_read_config32(dev, 0xf8);
dword |= 12;
- pci_conf1_write_config32(dev, 0xf8, dword);
+ pci_write_config32(dev, 0xf8, dword);
#ifdef CONFIG_PCI_ROM_RUN
pci_dev_init(dev);
#endif
Modified: coreboot-v3/southbridge/nvidia/mcp55/lpc.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/southbridge/nvidia/mcp55/lpc.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -144,10 +144,10 @@
u32 dword;
/* IO APIC initialization */
- byte = pci_conf1_read_config8(dev, 0x74);
+ byte = pci_read_config8(dev, 0x74);
byte |= (1<<0); // enable APIC
- pci_conf1_write_config8(dev, 0x74, byte);
- dword = pci_conf1_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
+ pci_write_config8(dev, 0x74, byte);
+ dword = pci_read_config32(dev, PCI_BASE_ADDRESS_1); // 0x14
setup_ioapic(dword, master);
}
@@ -162,8 +162,8 @@
{
unsigned long hpet_address;
- pci_conf1_write_config32(dev,0x44, 0xfed00001);
- hpet_address=pci_conf1_read_config32(dev,0x44)& 0xfffffffe;
+ pci_write_config32(dev,0x44, 0xfed00001);
+ hpet_address=pci_read_config32(dev,0x44)& 0xfffffffe;
printk(BIOS_DEBUG, "enabling HPET @0x%x\n", hpet_address);
}
#endif
@@ -180,20 +180,20 @@
#warning posted memory write enable disabled in mcp55 lpc?
#if 0
/* posted memory write enable */
- byte = pci_conf1_read_config8(dev, 0x46);
- pci_conf1_write_config8(dev, 0x46, byte | (1<<0));
+ byte = pci_read_config8(dev, 0x46);
+ pci_write_config8(dev, 0x46, byte | (1<<0));
#endif
/* power after power fail */
#if 1
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
- byte = pci_conf1_read_config8(dev, PREVIOUS_POWER_STATE);
+ byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
byte |= 0x40;
}
- pci_conf1_write_config8(dev, PREVIOUS_POWER_STATE, byte);
+ pci_write_config8(dev, PREVIOUS_POWER_STATE, byte);
printk(BIOS_INFO, "set power %s after power fail\n", on?"on":"off");
#endif
/* Throttle the CPU speed down for testing */
@@ -202,7 +202,7 @@
if(on) {
u16 pm10_bar;
u32 dword;
- pm10_bar = (pci_conf1_read_config16(dev, 0x60)&0xff00);
+ pm10_bar = (pci_read_config16(dev, 0x60)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
dword = inl(pm10_bar + 0x10);
on = 8-on;
@@ -213,16 +213,16 @@
#if 0
// default is enabled
/* Enable Port 92 fast reset */
- byte = pci_conf1_read_config8(dev, 0xe8);
+ byte = pci_read_config8(dev, 0xe8);
byte |= ~(1 << 3);
- pci_conf1_write_config8(dev, 0xe8, byte);
+ pci_write_config8(dev, 0xe8, byte);
#endif
/* Enable Error reporting */
/* Set up sync flood detected */
- byte = pci_conf1_read_config8(dev, 0x47);
+ byte = pci_read_config8(dev, 0x47);
byte |= (1 << 1);
- pci_conf1_write_config8(dev, 0x47, byte);
+ pci_write_config8(dev, 0x47, byte);
/* Set up NMI on errors */
byte = inb(0x70); // RTC70
@@ -286,7 +286,7 @@
int i;
int var_num = 0;
- reg = pci_conf1_read_config32(dev, 0xa0);
+ reg = pci_read_config32(dev, 0xa0);
for (link = 0; link < dev->links; link++) {
struct device *child;
@@ -324,9 +324,9 @@
}
}
}
- pci_conf1_write_config32(dev, 0xa0, reg);
+ pci_write_config32(dev, 0xa0, reg);
for(i=0;i<var_num;i++) {
- pci_conf1_write_config32(dev, 0xa8 + i*4, reg_var[i]);
+ pci_write_config32(dev, 0xa8 + i*4, reg_var[i]);
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/mcp55.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-10-01 06:47:51 UTC
(rev 876)
+++ coreboot-v3/southbridge/nvidia/mcp55/mcp55.c 2008-10-01 07:23:05 UTC
(rev 877)
@@ -52,7 +52,7 @@
(lpc_dev->id.pci.device > PCI_DEVICE_ID_NVIDIA_MCP55_PRO)
) ) {
u32 id;
- id = pci_conf1_read_config32(lpc_dev, PCI_VENDOR_ID);
+ id = pci_read_config32(lpc_dev, PCI_VENDOR_ID);
if ( (id < (PCI_VENDOR_ID_NVIDIA |
(PCI_DEVICE_ID_NVIDIA_MCP55_LPC << 16))) ||
(id > (PCI_VENDOR_ID_NVIDIA |
(PCI_DEVICE_ID_NVIDIA_MCP55_PRO << 16)))
) {
@@ -82,7 +82,7 @@
/* sorry. Again, anonymous unions etc. would make this easier. */
if(dev->id.pci.device==0x0000) {
- vendorid = pci_conf1_read_config32(dev, PCI_VENDOR_ID);
+ vendorid = pci_read_config32(dev, PCI_VENDOR_ID);
deviceid = (vendorid>>16) & 0xffff;
// vendorid &= 0xffff;
} else {
@@ -180,14 +180,14 @@
if(!sm_dev) return;
if ( sm_dev ) {
- reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
+ reg_old = reg = pci_read_config32(sm_dev, 0xe4);
if (!dev->enabled) { //disable it
reg |= (1<<index2);
}
if (reg != reg_old) {
- pci_conf1_write_config32(sm_dev, 0xe4, reg);
+ pci_write_config32(sm_dev, 0xe4, reg);
}
}
@@ -199,14 +199,14 @@
if ( index == 0) { // for LPC
// expose ioapic base
- byte = pci_conf1_read_config8(lpc_dev, 0x74);
+ byte = pci_read_config8(lpc_dev, 0x74);
byte |= ((1<<1)); // expose the BAR
- pci_conf1_write_config8(dev, 0x74, byte);
+ pci_write_config8(dev, 0x74, byte);
// expose trap base
- byte = pci_conf1_read_config8(lpc_dev, 0xdd);
+ byte = pci_read_config8(lpc_dev, 0xdd);
byte |= ((1<<0)|(1<<3)); // expose the BAR and enable write
- pci_conf1_write_config8(dev, 0xdd, byte);
+ pci_write_config8(dev, 0xdd, byte);
return;
@@ -216,16 +216,16 @@
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
- final_reg = pci_conf1_read_config32(sm_dev, 0xe8);
+ final_reg = pci_read_config32(sm_dev, 0xe8);
final_reg &=
~((1<<16)|(1<<8)|(1<<20)|(1<<14)|(1<<22)|(1<<18)|(1<<17)|(1<<15)|(1<<11)|(1<<10)|(1<<9));
- pci_conf1_write_config32(sm_dev, 0xe8, final_reg); //enable all
at first
+ pci_write_config32(sm_dev, 0xe8, final_reg); //enable all at
first
#if 0
- reg_old = reg = pci_conf1_read_config32(sm_dev, 0xe4);
+ reg_old = reg = pci_read_config32(sm_dev, 0xe4);
// reg |= (1<<0);
reg &= ~(0x3f<<4);
if (reg != reg_old) {
printk_debug("mcp55.c pcie enabled\n");
- pci_conf1_write_config32(sm_dev, 0xe4, reg);
+ pci_write_config32(sm_dev, 0xe4, reg);
}
#endif
}
@@ -238,9 +238,9 @@
if(index == 9 ) { //NIC1 is the final, We need update final reg to 0xe8
sm_dev = dev_find_slot(dev->bus->secondary, devfn + 1);
if(!sm_dev) return;
- reg_old = pci_conf1_read_config32(sm_dev, 0xe8);
+ reg_old = pci_read_config32(sm_dev, 0xe8);
if (final_reg != reg_old) {
- pci_conf1_write_config32(sm_dev, 0xe8, final_reg);
+ pci_write_config32(sm_dev, 0xe8, final_reg);
}
}
@@ -251,7 +251,7 @@
void mcp55_pci_dev_set_subsystem(struct device *dev, unsigned int vendor,
unsigned int device)
{
- pci_conf1_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
+ pci_write_config32(dev, PCI_MCP55_SUBSYSTEM_VENDOR_ID,
((device & 0xffff) << 16) | (vendor & 0xffff));
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/pci.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/southbridge/nvidia/mcp55/pci.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -43,23 +43,23 @@
#endif
/* System error enable */
- dword = pci_conf1_read_config32(dev, 0x04);
+ dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */
- pci_conf1_write_config32(dev, 0x04, dword);
+ pci_write_config32(dev, 0x04, dword);
#if 1
//only need (a01,xx]
- word = pci_conf1_read_config16(dev, 0x48);
+ word = pci_read_config16(dev, 0x48);
word |= (1<<0); /* MRL2MRM */
word |= (1<<2); /* MR2MRM */
- pci_conf1_write_config16(dev, 0x48, word);
+ pci_write_config16(dev, 0x48, word);
#endif
#if 1
- dword = pci_conf1_read_config32(dev, 0x4c);
+ dword = pci_read_config32(dev, 0x4c);
dword |= 0x00440000; /*TABORT_SER_ENABLE Park Last Enable.*/
- pci_conf1_write_config32(dev, 0x4c, dword);
+ pci_write_config32(dev, 0x4c, dword);
#endif
#ifdef CONFIG_PCI_64BIT_PREF_MEM
@@ -84,7 +84,7 @@
printk(BIOS_DEBUG, "dev_root mem base = 0x%010Lx\n",
dev_root.resource[1].base);
#endif
printk(BIOS_DEBUG, "[0x50] <-- 0x%08x\n", dword);
- pci_conf1_write_config32(dev, 0x50, dword); //TOM
+ pci_write_config32(dev, 0x50, dword); //TOM
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/pcie.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/southbridge/nvidia/mcp55/pcie.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -39,10 +39,10 @@
u32 dword;
/* System error enable */
- dword = pci_conf1_read_config32(dev, 0x04);
+ dword = pci_read_config32(dev, 0x04);
dword |= (1<<8); /* System error enable */
dword |= (1<<30); /* Clear possible errors */
- pci_conf1_write_config32(dev, 0x04, dword);
+ pci_write_config32(dev, 0x04, dword);
}
Modified: coreboot-v3/southbridge/nvidia/mcp55/sata.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/southbridge/nvidia/mcp55/sata.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -40,7 +40,7 @@
struct southbridge_nvidia_mcp55_sata_config *conf =
(struct southbridge_nvidia_mcp55_sata_config
*)dev->device_configuration;
- dword = pci_conf1_read_config32(dev, 0x50);
+ dword = pci_read_config32(dev, 0x50);
/* Ensure prefetch is disabled */
dword &= ~((1 << 15) | (1 << 13));
if(conf) {
@@ -62,11 +62,11 @@
dword &= ~(0x1f<<24);
dword |= (0x15<<24);
#endif
- pci_conf1_write_config32(dev, 0x50, dword);
+ pci_write_config32(dev, 0x50, dword);
- dword = pci_conf1_read_config32(dev, 0xf8);
+ dword = pci_read_config32(dev, 0xf8);
dword |= 2;
- pci_conf1_write_config32(dev, 0xf8, dword);
+ pci_write_config32(dev, 0xf8, dword);
}
struct device_operations mcp55_sata = {
Modified: coreboot-v3/southbridge/nvidia/mcp55/usb2.c
===================================================================
--- coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-10-01 06:47:51 UTC (rev
876)
+++ coreboot-v3/southbridge/nvidia/mcp55/usb2.c 2008-10-01 07:23:05 UTC (rev
877)
@@ -41,9 +41,9 @@
static void usb2_init(struct device *dev)
{
u32 dword;
- dword = pci_conf1_read_config32(dev, 0xf8);
+ dword = pci_read_config32(dev, 0xf8);
dword |= 40;
- pci_conf1_write_config32(dev, 0xf8, dword);
+ pci_write_config32(dev, 0xf8, dword);
}
static void usb2_set_resources(struct device *dev)
--
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