Author: myles
Date: 2008-10-02 21:21:30 +0200 (Thu, 02 Oct 2008)
New Revision: 3633
Modified:
trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h
trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h
trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
Log:
Whitespace cleanup (trivial).
Signed-off-by: Myles Watson <[EMAIL PROTECTED]>
Acked-by: Myles Watson <[EMAIL PROTECTED]>
Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h 2008-10-02
19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397.h 2008-10-02
19:21:30 UTC (rev 3633)
@@ -1,7 +1,7 @@
-#define LPC47B397_FDC 0 /* Floppy */
-#define LPC47B397_PP 3 /* Parallel Port */
-#define LPC47B397_SP1 4 /* Com1 */
-#define LPC47B397_SP2 5 /* Com2 */
-#define LPC47B397_KBC 7 /* Keyboard & Mouse */
-#define LPC47B397_HWM 8 /* HW Monitor */
-#define LPC47B397_RT 10 /* Runtime reg*/
+#define LPC47B397_FDC 0 /* Floppy */
+#define LPC47B397_PP 3 /* Parallel Port */
+#define LPC47B397_SP1 4 /* Com1 */
+#define LPC47B397_SP2 5 /* Com2 */
+#define LPC47B397_KBC 7 /* Keyboard & Mouse */
+#define LPC47B397_HWM 8 /* HW Monitor */
+#define LPC47B397_RT 10 /* Runtime reg*/
Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_gpio.c
2008-10-02 19:21:30 UTC (rev 3633)
@@ -2,9 +2,10 @@
{
outb(value,iobase+offset);
}
+
static unsigned lpc47b397_gpio_offset_in(unsigned iobase, unsigned offset)
{
- return inb(iobase+offset);
+ return inb(iobase+offset);
}
//for GP60-GP64, GP66-GP85
@@ -13,13 +14,13 @@
static void lpc47b397_gpio_index_out(unsigned iobase, unsigned index, unsigned
value)
{
- outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
+ outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
outb(value, iobase+LPC47B397_GPIO_CNTL_DATA);
}
+
static unsigned lpc47b397_gpio_index_in(unsigned iobase, unsigned index)
{
outb(index,iobase+LPC47B397_GPIO_CNTL_INDEX);
- return inb(iobase+LPC47B397_GPIO_CNTL_DATA);
+ return inb(iobase+LPC47B397_GPIO_CNTL_DATA);
}
-
Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/lpc47b397_early_serial.c
2008-10-02 19:21:30 UTC (rev 3633)
@@ -3,12 +3,14 @@
static inline void pnp_enter_conf_state(device_t dev) {
unsigned port = dev>>8;
- outb(0x55, port);
+ outb(0x55, port);
}
+
static void pnp_exit_conf_state(device_t dev) {
unsigned port = dev>>8;
- outb(0xaa, port);
+ outb(0xaa, port);
}
+
static void lpc47b397_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_conf_state(dev);
Modified: trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2008-10-02
19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/smsc/lpc47b397/superio.c 2008-10-02
19:21:30 UTC (rev 3633)
@@ -1,7 +1,7 @@
/* Copyright 2000 AG Electronics Ltd. */
/* Copyright 2003-2004 Linux Networx */
-/* Copyright 2004 Tyan
- */
+/* Copyright 2004 Tyan
+ */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
@@ -20,32 +20,32 @@
static void pnp_enter_conf_state(device_t dev) {
- outb(0x55, dev->path.u.pnp.port);
+ outb(0x55, dev->path.u.pnp.port);
}
static void pnp_exit_conf_state(device_t dev) {
- outb(0xaa, dev->path.u.pnp.port);
+ outb(0xaa, dev->path.u.pnp.port);
}
static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t
value)
{
- outb(reg, port_base);
- outb(value, port_base + 1);
+ outb(reg, port_base);
+ outb(value, port_base + 1);
}
static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
{
- outb(reg, port_base);
- return inb(port_base + 1);
+ outb(reg, port_base);
+ return inb(port_base + 1);
}
static void enable_hwm_smbus(device_t dev) {
/* enable SensorBus register access */
- uint8_t reg, value;
- reg = 0xf0;
- value = pnp_read_config(dev, reg);
- value |= 0x01;
- pnp_write_config(dev, reg, value);
-}
+ uint8_t reg, value;
+ reg = 0xf0;
+ value = pnp_read_config(dev, reg);
+ value |= 0x01;
+ pnp_write_config(dev, reg, value);
+}
static void lpc47b397_init(device_t dev)
@@ -57,7 +57,7 @@
}
conf = dev->chip_info;
switch(dev->path.u.pnp.device) {
- case LPC47B397_SP1:
+ case LPC47B397_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
@@ -71,51 +71,51 @@
init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
}
-
+
}
void lpc47b397_pnp_set_resources(device_t dev)
{
- pnp_enter_conf_state(dev);
+ pnp_enter_conf_state(dev);
pnp_set_resources(dev);
#if 0
- dump_pnp_device(dev);
+ dump_pnp_device(dev);
#endif
-
- pnp_exit_conf_state(dev);
-
-}
-
+
+ pnp_exit_conf_state(dev);
+
+}
+
void lpc47b397_pnp_enable_resources(device_t dev)
-{
+{
- pnp_enter_conf_state(dev);
+ pnp_enter_conf_state(dev);
- pnp_enable_resources(dev);
+ pnp_enable_resources(dev);
- switch(dev->path.u.pnp.device) {
- case LPC47B397_HWM:
- printk_debug("lpc47b397 SensorBus Register Access
enabled\r\n");
+ switch(dev->path.u.pnp.device) {
+ case LPC47B397_HWM:
+ printk_debug("lpc47b397 SensorBus Register Access enabled\r\n");
pnp_set_logical_device(dev);
- enable_hwm_smbus(dev);
- break;
- }
+ enable_hwm_smbus(dev);
+ break;
+ }
-#if 0
- dump_pnp_device(dev);
+#if 0
+ dump_pnp_device(dev);
#endif
- pnp_exit_conf_state(dev);
+ pnp_exit_conf_state(dev);
}
void lpc47b397_pnp_enable(device_t dev)
{
- pnp_enter_conf_state(dev);
+ pnp_enter_conf_state(dev);
pnp_set_logical_device(dev);
@@ -126,8 +126,8 @@
pnp_set_enable(dev, 0);
}
- pnp_exit_conf_state(dev);
-
+ pnp_exit_conf_state(dev);
+
}
static struct device_operations ops = {
@@ -149,60 +149,60 @@
static int lsmbus_read_byte(device_t dev, uint8_t address)
{
- unsigned device;
- struct resource *res;
+ unsigned device;
+ struct resource *res;
int result;
- device = dev->path.u.i2c.device;
+ device = dev->path.u.i2c.device;
- res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
+ res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
-
+
result = pnp_read_index(res->base+SB_INDEX, address); // we only read
it one byte one time
-
- return result;
+
+ return result;
}
static int lsmbus_write_byte(device_t dev, uint8_t address, uint8_t val)
-{
- unsigned device;
- struct resource *res;
-
- device = dev->path.u.i2c.device;
+{
+ unsigned device;
+ struct resource *res;
+
+ device = dev->path.u.i2c.device;
res = find_resource(get_pbus_smbus(dev)->dev, PNP_IDX_IO0);
- pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
+ pnp_write_index(res->base+HWM_INDEX, 0, device); // why 0?
- pnp_write_index(res->base+SB_INDEX, address, val); // we only write it
one byte one time
-
- return 0;
+ pnp_write_index(res->base+SB_INDEX, address, val); // we only write it
one byte one time
+
+ return 0;
}
static struct smbus_bus_operations lops_smbus_bus = {
-// .recv_byte = lsmbus_recv_byte,
-// .send_byte = lsmbus_send_byte,
- .read_byte = lsmbus_read_byte,
- .write_byte = lsmbus_write_byte,
+// .recv_byte = lsmbus_recv_byte,
+// .send_byte = lsmbus_send_byte,
+ .read_byte = lsmbus_read_byte,
+ .write_byte = lsmbus_write_byte,
};
static struct device_operations ops_hwm = {
- .read_resources = pnp_read_resources,
- .set_resources = lpc47b397_pnp_set_resources,
- .enable_resources = lpc47b397_pnp_enable_resources,
- .enable = lpc47b397_pnp_enable,
- .init = lpc47b397_init,
+ .read_resources = pnp_read_resources,
+ .set_resources = lpc47b397_pnp_set_resources,
+ .enable_resources = lpc47b397_pnp_enable_resources,
+ .enable = lpc47b397_pnp_enable,
+ .init = lpc47b397_init,
.scan_bus = scan_static_bus,
.ops_smbus_bus = &lops_smbus_bus,
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {
0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, LPC47B397_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47B397_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, LPC47B397_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47B397_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, LPC47B397_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {
0x7ff, 0 }, { 0x7ff, 0x4}, },
{ &ops_hwm, LPC47B397_HWM, PNP_IO0, { 0x7f0, 0 }, },
- { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, },
+ { &ops, LPC47B397_RT, PNP_IO0, { 0x780, 0 }, },
};
static void enable_dev(struct device *dev)
Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2008-10-02
19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/superio.c 2008-10-02
19:21:30 UTC (rev 3633)
@@ -1,6 +1,6 @@
/* Copyright 2000 AG Electronics Ltd. */
/* Copyright 2003-2004 Linux Networx */
-/* Copyright 2004 Tyan
+/* Copyright 2004 Tyan
By LYH change from PC87360 */
/* This code is distributed without warranty under the GPL v2 (see COPYING) */
@@ -18,27 +18,27 @@
#include "w83627hf.h"
-static void pnp_enter_ext_func_mode(device_t dev)
+static void pnp_enter_ext_func_mode(device_t dev)
{
- outb(0x87, dev->path.u.pnp.port);
- outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.u.pnp.port);
+ outb(0x87, dev->path.u.pnp.port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+static void pnp_exit_ext_func_mode(device_t dev)
{
- outb(0xaa, dev->path.u.pnp.port);
+ outb(0xaa, dev->path.u.pnp.port);
}
static void pnp_write_index(unsigned long port_base, uint8_t reg, uint8_t
value)
{
- outb(reg, port_base);
- outb(value, port_base + 1);
+ outb(reg, port_base);
+ outb(value, port_base + 1);
}
static uint8_t pnp_read_index(unsigned long port_base, uint8_t reg)
{
- outb(reg, port_base);
- return inb(port_base + 1);
-}
+ outb(reg, port_base);
+ return inb(port_base + 1);
+}
static void enable_hwm_smbus(device_t dev) {
/* set the pin 91,92 as I2C bus */
@@ -56,14 +56,14 @@
get_option(&power_on, "power_on_after_fail");
pnp_enter_ext_func_mode(dev);
- pnp_write_index(dev->path.u.pnp.port,7,0x0a);
+ pnp_write_index(dev->path.u.pnp.port,7,0x0a);
value = pnp_read_config(dev, 0xE4);
value &= ~(3<<5);
if(power_on) {
value |= (1<<5);
}
pnp_write_config(dev, 0xE4, value);
- pnp_exit_ext_func_mode(dev);
+ pnp_exit_ext_func_mode(dev);
}
static void init_hwm(unsigned long base)
@@ -72,16 +72,16 @@
int i;
unsigned hwm_reg_values[] = {
-/* reg mask data */
- 0x40, 0xff, 0x81, /* start HWM */
- 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
- 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus
base to 0x94>>1 */
- 0x4e, 0x80, 0x00,
- 0x43, 0x00, 0xff,
- 0x44, 0x00, 0x3f,
- 0x4c, 0xbf, 0x18,
- 0x4d, 0xff, 0x80 /* turn off beep */
-
+/* reg mask data */
+ 0x40, 0xff, 0x81, /* start HWM */
+ 0x48, 0xaa, 0x2a, /* set SMBus base to 0x54>>1 */
+ 0x4a, 0x21, 0x21, /* set T2 SMBus base to 0x92>>1 and T3 SMBus
base to 0x94>>1 */
+ 0x4e, 0x80, 0x00,
+ 0x43, 0x00, 0xff,
+ 0x44, 0x00, 0x3f,
+ 0x4c, 0xbf, 0x18,
+ 0x4d, 0xff, 0x80 /* turn off beep */
+
};
for(i = 0; i< ARRAY_SIZE(hwm_reg_values); i+=3 ) {
@@ -105,7 +105,7 @@
}
conf = dev->chip_info;
switch(dev->path.u.pnp.device) {
- case W83627HF_SP1:
+ case W83627HF_SP1:
res0 = find_resource(dev, PNP_IDX_IO0);
init_uart8250(res0->base, &conf->com1);
break;
@@ -118,50 +118,50 @@
res1 = find_resource(dev, PNP_IDX_IO1);
init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
break;
- case W83627HF_HWM:
- res0 = find_resource(dev, PNP_IDX_IO0);
+ case W83627HF_HWM:
+ res0 = find_resource(dev, PNP_IDX_IO0);
#define HWM_INDEX_PORT 5
- init_hwm(res0->base + HWM_INDEX_PORT);
- break;
- case W83627HF_ACPI:
- init_acpi(dev);
- break;
+ init_hwm(res0->base + HWM_INDEX_PORT);
+ break;
+ case W83627HF_ACPI:
+ init_acpi(dev);
+ break;
}
}
void w83627hf_pnp_set_resources(device_t dev)
{
- pnp_enter_ext_func_mode(dev);
+ pnp_enter_ext_func_mode(dev);
pnp_set_resources(dev);
- pnp_exit_ext_func_mode(dev);
-
-}
-
+ pnp_exit_ext_func_mode(dev);
+
+}
+
void w83627hf_pnp_enable_resources(device_t dev)
-{
- pnp_enter_ext_func_mode(dev);
- pnp_enable_resources(dev);
- switch(dev->path.u.pnp.device) {
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ switch(dev->path.u.pnp.device) {
case W83627HF_HWM:
printk_debug("w83627hf hwm smbus enabled\n");
enable_hwm_smbus(dev);
break;
}
- pnp_exit_ext_func_mode(dev);
+ pnp_exit_ext_func_mode(dev);
}
void w83627hf_pnp_enable(device_t dev)
{
- if (!dev->enabled) {
- pnp_enter_ext_func_mode(dev);
+ if (!dev->enabled) {
+ pnp_enter_ext_func_mode(dev);
- pnp_set_logical_device(dev);
- pnp_set_enable(dev, 0);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, 0);
- pnp_exit_ext_func_mode(dev);
- }
+ pnp_exit_ext_func_mode(dev);
+ }
}
static struct device_operations ops = {
@@ -173,18 +173,18 @@
};
static struct pnp_info pnp_dev_info[] = {
- { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
- { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- // No 4 { 0,},
- { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {
0x7ff, 0 }, { 0x7ff, 0x4}, },
- { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
- { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {
0x7ff, 0 }, {0x7fe, 0x4}, },
- { &ops, W83627HF_GPIO2, },
- { &ops, W83627HF_GPIO3, },
- { &ops, W83627HF_ACPI, },
- { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
+ { &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
+ { &ops, W83627HF_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627HF_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ // No 4 { 0,},
+ { &ops, W83627HF_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, {
0x7ff, 0 }, { 0x7ff, 0x4}, },
+ { &ops, W83627HF_CIR, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
+ { &ops, W83627HF_GAME_MIDI_GPIO1, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {
0x7ff, 0 }, {0x7fe, 0x4}, },
+ { &ops, W83627HF_GPIO2, },
+ { &ops, W83627HF_GPIO3, },
+ { &ops, W83627HF_ACPI, },
+ { &ops, W83627HF_HWM, PNP_IO0 | PNP_IRQ0, { 0xff8, 0 }, },
};
static void enable_dev(struct device *dev)
Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h 2008-10-02
19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf.h 2008-10-02
19:21:30 UTC (rev 3633)
@@ -18,10 +18,10 @@
#define W83627HF_GPEVR 0xf2
#define W83627HF_GPCFG2 0xf3
#define W83627HF_EXTCFG 0xf4
-#define W83627HF_IOEXT1A 0xf5
-#define W83627HF_IOEXT1B 0xf6
-#define W83627HF_IOEXT2A 0xf7
-#define W83627HF_IOEXT2B 0xf8
+#define W83627HF_IOEXT1A 0xf5
+#define W83627HF_IOEXT1B 0xf6
+#define W83627HF_IOEXT2A 0xf7
+#define W83627HF_IOEXT2B 0xf8
#define W83627HF_GPDO_0 0x00
#define W83627HF_GPDI_0 0x01
@@ -40,26 +40,26 @@
#define W83627HF_GPDO_5 0x0e
#define W83627HF_GPDI_5 0x0f
#define W83627HF_GPDO_6 0x10
-#define W83627HF_GPDO_7A 0x11
-#define W83627HF_GPDO_7B 0x12
-#define W83627HF_GPDO_7C 0x13
-#define W83627HF_GPDO_7D 0x14
-#define W83627HF_GPDI_7A 0x15
-#define W83627HF_GPDI_7B 0x16
-#define W83627HF_GPDI_7C 0x17
-#define W83627HF_GPDI_7D 0x18
+#define W83627HF_GPDO_7A 0x11
+#define W83627HF_GPDO_7B 0x12
+#define W83627HF_GPDO_7C 0x13
+#define W83627HF_GPDO_7D 0x14
+#define W83627HF_GPDI_7A 0x15
+#define W83627HF_GPDI_7B 0x16
+#define W83627HF_GPDI_7C 0x17
+#define W83627HF_GPDI_7D 0x18
#define W83627HF_XIOCNF 0xf0
-#define W83627HF_XIOBA1H 0xf1
-#define W83627HF_XIOBA1L 0xf2
+#define W83627HF_XIOBA1H 0xf1
+#define W83627HF_XIOBA1L 0xf2
#define W83627HF_XIOSIZE1 0xf3
-#define W83627HF_XIOBA2H 0xf4
-#define W83627HF_XIOBA2L 0xf5
+#define W83627HF_XIOBA2H 0xf4
+#define W83627HF_XIOBA2L 0xf5
#define W83627HF_XIOSIZE2 0xf6
#define W83627HF_XMEMCNF1 0xf7
#define W83627HF_XMEMCNF2 0xf8
-#define W83627HF_XMEMBAH 0xf9
-#define W83627HF_XMEMBAL 0xfa
+#define W83627HF_XMEMBAH 0xf9
+#define W83627HF_XMEMBAL 0xfa
#define W83627HF_XMEMSIZE 0xfb
#define W83627HF_XIRQMAP1 0xfc
#define W83627HF_XIRQMAP2 0xfd
Modified: trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
===================================================================
--- trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
2008-10-02 19:20:22 UTC (rev 3632)
+++ trunk/coreboot-v2/src/superio/winbond/w83627hf/w83627hf_early_serial.c
2008-10-02 19:21:30 UTC (rev 3633)
@@ -1,17 +1,19 @@
#include <arch/romcc_io.h>
#include "w83627hf.h"
-static inline void pnp_enter_ext_func_mode(device_t dev)
+static inline void pnp_enter_ext_func_mode(device_t dev)
{
unsigned port = dev>>8;
- outb(0x87, port);
- outb(0x87, port);
+ outb(0x87, port);
+ outb(0x87, port);
}
-static void pnp_exit_ext_func_mode(device_t dev)
+
+static void pnp_exit_ext_func_mode(device_t dev)
{
unsigned port = dev>>8;
- outb(0xaa, port);
+ outb(0xaa, port);
}
+
static void w83627hf_enable_serial(device_t dev, unsigned iobase)
{
pnp_enter_ext_func_mode(dev);
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
