This is initial support for dbm690t. It does not build, in fact if fails as follows: Makefile:115: mainboard//Makefile: No such file or directory make: *** No rule to make target `mainboard//Makefile'. Stop. Help! not yet signed off :-) Index: mainboard/amd/dbm690t/mainboard.h =================================================================== --- mainboard/amd/dbm690t/mainboard.h (revision 0) +++ mainboard/amd/dbm690t/mainboard.h (revision 0) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * Constants that are mainboard-defined and do not belong in Kconfig. + * We really do not want this stuff to be visible -- it will make it appear that they can be + * changed, and they can not. + * + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#default DIMM_SUPPORT=0x0204 #DDR2 and REG, S1G1 + +#define DIMM_SOCKETS 2 +#define NODE_NUMS 2 +#define CPU_SOCKET_TYPE SOCKET_S1G1 +#define MEM_TRAIN_SEQ 0 /* for now */ +#define HW_MEM_HOLE_SIZE_AUTO_INC 0 +#define HW_MEM_HOLE_SIZEK 0x100000 +#define HT_CHAIN_UNITID_BASE 0x0 +#define HT_CHAIN_END_UNITID_BASE 0x6 +#define SB_HT_CHAIN_ON_BUS0 1 +#define SB_HT_CHAIN_UNITID_OFFSET_ONLY 0 +#define ENABLE_APIC_EXT_ID 0 +#define LIFT_BSP_APIC_ID 1 +#define K8_SET_FIDVID 1 +/* MSR FIDVID_CTL and FIDVID_STATUS are shared by cores, + * so may don't need to do twice */ +#define K8_SET_FIDVID_CORE0_ONLY 1 + +/* architecture stuff which ought to be set "somewhere" "SOMEHOW" */ +/* preferably by asking the CPU, not be a DEFINE! */ +#define CPU_ADDR_BITS 40 Index: mainboard/amd/dbm690t/initram.c =================================================================== --- mainboard/amd/dbm690t/initram.c (revision 0) +++ mainboard/amd/dbm690t/initram.c (revision 0) @@ -0,0 +1,245 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2007 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#define _MAINOBJECT + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define RC0 ((1<<0)<<8) +#define RC1 ((1<<1)<<8) +#define RC2 ((1<<2)<<8) +#define RC3 ((1<<3)<<8) + +#define DIMM0 0x50 +#define DIMM1 0x51 +#define DIMM2 0x52 +#define DIMM3 0x53 +#define DIMM4 0x54 +#define DIMM5 0x55 +#define DIMM6 0x56 +#define DIMM7 0x57 + +/* this code is very mainboard dependent, sadly. */ +/** + * call the amd 8111 memreset_setup_amd8111 function to jam the GPIOs to reset memory. + */ +static void memreset_setup(void) +{ +} + +/** + * this is a no op on this platform. + */ +void memreset(int controllers, const struct mem_controller *ctrl) +{ +} + +void activate_spd_rom(const struct mem_controller *ctrl) +{ +} + +/** + * read a byte from spd. + * @param device device to read from + * @param address address in the spd ROM + * @return the value of the byte at that address. + */ +u8 spd_read_byte(u16 device, u8 address) +{ + int smbus_read_byte(u16 device, u16 address); + return smbus_read_byte(device, address); +} + +/** + * main for initram for the AMD DBM690T + * @param init_detected Used to indicate that we have been started via init + * @returns 0 on success + * The purpose of this code is to not only get ram going, but get any other cpus/cores going. + * The two activities are very tightly connected and not really seperable. + * The BSP (boot strap processor) Core 0 (BSC) is responsible for all training or all sockets. Note that + * this need not be socket 0; one great strength of coreboot, as opposed to other BIOSes, is that it could + * always boot with with a CPU in any socket, and even with empty sockets (as opposed to, e.g., the BIOS + * that came installed on the Sun Ultra 40, which would freeze if one CPU were not installed). + * The bringup proceeds in several sections. The cool part is that this code is run by all CPUs, and + * control flow is managed by seeing which CPU we are -- BSP or AP? + * + */ +/* + * init_detected is used to determine if we did a soft reset as required by a reprogramming of the + * hypertransport links. If we did this kind of reset, bit 11 will be set in the MTRRdefType_MSR MSR. + * That may seem crazy, but there are not lots of places to hide a bit when the CPU does a reset. + * This value is picked up in assembly, or it should be. + */ +int main(void) +{ + /* sure, we could put this in a .h. It's called precisely once, from this one + * place. And it only relates to the initram stage. I think I'll leave it here. + * That way we can see the definition without grepping the source tree. + */ + void enable_smbus(void); + void enable_fid_change_on_sb(u16 sbbusn, u16 sbdn); + void soft_reset_x(unsigned sbbusn, unsigned sbdn); + int cpu_init_detected(unsigned int nodeid); + u32 init_detected; + static const u16 spd_addr[] = { + //first node + RC0 | DIMM0, RC0 | DIMM2, 0, 0, + RC0 | DIMM1, RC0 | DIMM3, 0, 0, +#if CONFIG_MAX_PHYSICAL_CPUS > 1 + //second node + RC1 | DIMM0, RC1 | DIMM2, RC1 | DIMM4, RC1 | DIMM6, + RC1 | DIMM1, RC1 | DIMM3, RC1 | DIMM5, RC1 | DIMM7, +#endif +#if CONFIG_MAX_PHYSICAL_CPUS > 2 + // third node + RC2 | DIMM0, RC2 | DIMM2, 0, 0, + RC2 | DIMM1, RC2 | DIMM3, 0, 0, + // four node + RC3 | DIMM0, RC3 | DIMM2, RC3 | DIMM4, RC3 | DIMM6, + RC3 | DIMM1, RC3 | DIMM3, RC3 | DIMM5, RC3 | DIMM7, +#endif + + }; + + struct sys_info *sysinfo; + int needs_reset; + unsigned bsp_apicid = 0; + struct msr msr; + struct node_core_id me; + + me = get_node_core_id(); + printk(BIOS_DEBUG, "Hi there from stage1, cpu%d, core%d\n", me.nodeid, me.coreid); + post_code(POST_START_OF_MAIN); + sysinfo = &(global_vars()->sys_info); +resource map + init_detected = cpu_init_detected(me.nodeid); + printk(BIOS_DEBUG, "init_detected: %d\n", init_detected); + /* well, here we are. For starters, we need to know if this is cpu0 core0. + * cpu0 core 0 will do all the DRAM setup. + */ + bsp_apicid = init_cpus(init_detected, sysinfo); + +// dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE); + +#if 0 + dump_pci_device(PCI_DEV(0, 0x18, 0)); + dump_pci_device(PCI_DEV(0, 0x19, 0)); +#endif + + printk(BIOS_DEBUG, "bsp_apicid=%02x\n", bsp_apicid); + +#if MEM_TRAIN_SEQ == 1 + set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram +#endif + setup_coherent_ht_domain(); // routing table and start other core0 + + wait_all_core0_started(); +#if CONFIG_LOGICAL_CPUS==1 + // It is said that we should start core1 after all core0 launched + /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, + * So here need to make sure last core0 is started, esp for two way system, + * (there may be apic id conflicts in that case) + */ + start_all_cores(); + wait_all_other_cores_started(bsp_apicid); +#endif + + /* it will set up chains and store link pair for optimization later */ + ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn + +#if 0 + //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); +#endif + + /* run _early_setup before soft-reset. */ + rs690_early_setup(); + sb600_early_setup(); + + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", + msr.hi, msr.lo); + + enable_fid_change(); + + enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + init_fidvid_bsp(bsp_apicid); + + msr = rdmsr(FIDVID_STATUS); + printk(BIOS_DEBUG, "begin msr fid, vid %08x:%08x\n", + msr.hi, msr.lo); + +#if 1 + needs_reset = optimize_link_coherent_ht(); + needs_reset |= optimize_link_incoherent_ht(sysinfo); + + // fidvid change will issue one LDTSTOP and the HT change will be effective too + if (needs_reset) { + printk(BIOS_INFO, "ht reset -\r\n"); + soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); + } +#endif + allow_all_aps_stop(bsp_apicid); + + //It's the time to set ctrl in sysinfo now; + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); + + enable_smbus(); + + memreset_setup(); + + //do we need apci timer, tsc...., only debug need it for better output + /* all ap stopped? */ +// init_timer(); // Need to use TMICT to synconize FID/VID + + sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); + +#if 0 + print_pci_devices(); +#endif + +#if 0 +// dump_pci_devices(); + dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); + dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); +#endif + + rs690_before_pci_init(); + sb600_before_pci_init(); + printk(BIOS_DEBUG, "stage1 returns\n"); + return 0; +} Index: mainboard/amd/dbm690t/stage1.c =================================================================== --- mainboard/amd/dbm690t/stage1.c (revision 0) +++ mainboard/amd/dbm690t/stage1.c (revision 0) @@ -0,0 +1,322 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007 Advanced Micro Devices, Inc. + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* updated from dbm690T */ +static const struct rmap register_values[] = { + + /* Careful set limit registers before base registers which contain the enables */ + /* DRAM Limit i Registers + * F1:0x44 i = 0 + * F1:0x4C i = 1 + * F1:0x54 i = 2 + * F1:0x5C i = 3 + * F1:0x64 i = 4 + * F1:0x6C i = 5 + * F1:0x74 i = 6 + * F1:0x7C i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 3] Reserved + * [10: 8] Interleave select + * specifies the values of A[14:12] to use with interleave enable. + * [15:11] Reserved + * [31:16] DRAM Limit Address i Bits 39-24 + * This field defines the upper address bits of a 40 bit address + * that define the end of the DRAM region. + */ + PCM(0, 0x18, 1, 0x44, 0x0000f8f8, 0x00000000), + PCM(0, 0x18, 1, 0x4C, 0x0000f8f8, 0x00000001), + PCM(0, 0x18, 1, 0x54, 0x0000f8f8, 0x00000002), + PCM(0, 0x18, 1, 0x5C, 0x0000f8f8, 0x00000003), + PCM(0, 0x18, 1, 0x64, 0x0000f8f8, 0x00000004), + PCM(0, 0x18, 1, 0x6C, 0x0000f8f8, 0x00000005), + PCM(0, 0x18, 1, 0x74, 0x0000f8f8, 0x00000006), + PCM(0, 0x18, 1, 0x7C, 0x0000f8f8, 0x00000007), + /* DRAM Base i Registers + * F1:0x40 i = 0 + * F1:0x48 i = 1 + * F1:0x50 i = 2 + * F1:0x58 i = 3 + * F1:0x60 i = 4 + * F1:0x68 i = 5 + * F1:0x70 i = 6 + * F1:0x78 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 7: 2] Reserved + * [10: 8] Interleave Enable + * 000 = No interleave + * 001 = Interleave on A[12] (2 nodes) + * 010 = reserved + * 011 = Interleave on A[12] and A[14] (4 nodes) + * 100 = reserved + * 101 = reserved + * 110 = reserved + * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes) + * [15:11] Reserved + * [13:16] DRAM Base Address i Bits 39-24 + * This field defines the upper address bits of a 40-bit address + * that define the start of the DRAM region. + */ + PCM(0, 0x18, 1, 0x40, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x48, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x50, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x58, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x60, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x68, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x70, 0x0000f8fc, 0x00000000), + PCM(0, 0x18, 1, 0x78, 0x0000f8fc, 0x00000000), + + /* Memory-Mapped I/O Limit i Registers + * F1:0x84 i = 0 + * F1:0x8C i = 1 + * F1:0x94 i = 2 + * F1:0x9C i = 3 + * F1:0xA4 i = 4 + * F1:0xAC i = 5 + * F1:0xB4 i = 6 + * F1:0xBC i = 7 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = Reserved + * [ 6: 6] Reserved + * [ 7: 7] Non-Posted + * 0 = CPU writes may be posted + * 1 = CPU writes must be non-posted + * [31: 8] Memory-Mapped I/O Limit Address i (39-16) + * This field defines the upp adddress bits of a 40-bit address that + * defines the end of a memory-mapped I/O region n + */ + PCM(0, 0x18, 1, 0x84, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x8C, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x94, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0x9C, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xA4, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xAC, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xB4, 0x00000048, 0x00000000), + PCM(0, 0x18, 1, 0xBC, 0x00000048, 0x00ffff00), + + /* Memory-Mapped I/O Base i Registers + * F1:0x80 i = 0 + * F1:0x88 i = 1 + * F1:0x90 i = 2 + * F1:0x98 i = 3 + * F1:0xA0 i = 4 + * F1:0xA8 i = 5 + * F1:0xB0 i = 6 + * F1:0xB8 i = 7 + * [ 0: 0] Read Enable + * 0 = Reads disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes disabled + * 1 = Writes Enabled + * [ 2: 2] Cpu Disable + * 0 = Cpu can use this I/O range + * 1 = Cpu requests do not use this I/O range + * [ 3: 3] Lock + * 0 = base/limit registers i are read/write + * 1 = base/limit registers i are read-only + * [ 7: 4] Reserved + * [31: 8] Memory-Mapped I/O Base Address i (39-16) + * This field defines the upper address bits of a 40bit address + * that defines the start of memory-mapped I/O region i + */ + PCM(0, 0x18, 1, 0x80, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x88, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x90, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0x98, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA0, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xA8, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB0, 0x000000f0, 0x00000000), + PCM(0, 0x18, 1, 0xB8, 0x000000f0, 0x00fc0003), + + /* PCI I/O Limit i Registers + * F1:0xC4 i = 0 + * F1:0xCC i = 1 + * F1:0xD4 i = 2 + * F1:0xDC i = 3 + * [ 2: 0] Destination Node ID + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 3: 3] Reserved + * [ 5: 4] Destination Link ID + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 = reserved + * [11: 6] Reserved + * [24:12] PCI I/O Limit Address i + * This field defines the end of PCI I/O region n + * [31:25] Reserved + */ + PCM(0, 0x18, 1, 0xC4, 0xFE000FC8, 0x01fff000), + PCM(0, 0x18, 1, 0xCC, 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xD4, 0xFE000FC8, 0x00000000), + PCM(0, 0x18, 1, 0xDC, 0xFE000FC8, 0x00000000), + + /* PCI I/O Base i Registers + * F1:0xC0 i = 0 + * F1:0xC8 i = 1 + * F1:0xD0 i = 2 + * F1:0xD8 i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 3: 2] Reserved + * [ 4: 4] VGA Enable + * 0 = VGA matches Disabled + * 1 = matches all address < 64K and where A[9:0] is in the + * range 3B0-3BB or 3C0-3DF independen of the base & limit registers + * [ 5: 5] ISA Enable + * 0 = ISA matches Disabled + * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block + * from matching agains this base/limit pair + * [11: 6] Reserved + * [24:12] PCI I/O Base i + * This field defines the start of PCI I/O region n + * [31:25] Reserved + */ + PCM(0, 0x18, 1, 0xC0, 0xFE000FCC, 0x00000003), + PCM(0, 0x18, 1, 0xC8, 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD0, 0xFE000FCC, 0x00000000), + PCM(0, 0x18, 1, 0xD8, 0xFE000FCC, 0x00000000), + + /* Config Base and Limit i Registers + * F1:0xE0 i = 0 + * F1:0xE4 i = 1 + * F1:0xE8 i = 2 + * F1:0xEC i = 3 + * [ 0: 0] Read Enable + * 0 = Reads Disabled + * 1 = Reads Enabled + * [ 1: 1] Write Enable + * 0 = Writes Disabled + * 1 = Writes Enabled + * [ 2: 2] Device Number Compare Enable + * 0 = The ranges are based on bus number + * 1 = The ranges are ranges of devices on bus 0 + * [ 3: 3] Reserved + * [ 6: 4] Destination Node + * 000 = Node 0 + * 001 = Node 1 + * 010 = Node 2 + * 011 = Node 3 + * 100 = Node 4 + * 101 = Node 5 + * 110 = Node 6 + * 111 = Node 7 + * [ 7: 7] Reserved + * [ 9: 8] Destination Link + * 00 = Link 0 + * 01 = Link 1 + * 10 = Link 2 + * 11 - Reserved + * [15:10] Reserved + * [23:16] Bus Number Base i + * This field defines the lowest bus number in configuration region i + * [31:24] Bus Number Limit i + * This field defines the highest bus number in configuration regin i + */ + PCM(0, 0x18, 1, 0xE0, 0x0000FC88, 0x08000003), + PCM(0, 0x18, 1, 0xE4, 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xE8, 0x0000FC88, 0x00000000), + PCM(0, 0x18, 1, 0xEC, 0x0000FC88, 0x00000000), + }; + +#define SERIAL_IOBASE 0x3f8 + +void hardware_stage1(void) +{ +/* + void enumerate_ht_chain(void); + int max; + printk(BIOS_ERR, "Stage1: enable rom ...\n"); + max = ARRAY_SIZE(register_values); + setup_resource_map(register_values, max); + */ + /* Nothing special needs to be done to find bus 0 */ + /* Allow the HT devices to be found */ + enumerate_ht_chain(); + + /* sb600_lpc_port80(); */ + sb600_pci_port80(); + enable_rs690_dev8(); + sb600_lpc_init(); + + /* it8712f_enable_serial does not use its 1st parameter. */ + it8712f_enable_serial(0, TTYS0_BASE); + printk(BIOS_ERR, "Done.\n"); + post_code(POST_START_OF_MAIN); + +} + +void mainboard_pre_payload(void) +{ + banner(BIOS_DEBUG, "mainboard_pre_payload: done"); +} Index: mainboard/amd/dbm690t/resourcemap.c =================================================================== --- mainboard/amd/dbm690t/resourcemap.c (revision 0) +++ mainboard/amd/dbm690t/resourcemap.c (revision 0) @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2002 Linux NetworX + * Copyright (C) 2008 Ronald G. Minnich + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +/{ + mainboard_vendor = "AMD"; + mainboard_name = "Serengeti"; + cpus { }; + apic@0 { + }; + domain@0 { + /config/("northbridge/amd/k8/domain"); + pci@1,0{ + }; + /* guesses; we need a real lspci */ + pci0@18,0 { + /config/("northbridge/amd/k8/pci"); + pci0 { + /config/("southbridge/amd/sb600/sb600.dts"); + }; + }; + pci1@18,0 { + /config/("northbridge/amd/k8/pci"); + }; + pci2@18,0 { + /config/("northbridge/amd/k8/pci"); + /* just for illustrating link #2 */ + pci@2,0{ + }; + }; + pci@18,1 {}; + pci@18,2 {}; + pci@18,3 {}; + ioport@2e { + /config/("superio/ite/it8712f/dts"); + com1enable = "1"; + }; + }; +}; Index: mainboard/amd/dbm690t/Makefile =================================================================== --- mainboard/amd/dbm690t/Makefile (revision 0) +++ mainboard/amd/dbm690t/Makefile (revision 0) @@ -0,0 +1,50 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2006-2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + + +STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ + $(src)/mainboard/$(MAINBOARDDIR)/stage1.c \ + $(src)/mainboard/$(MAINBOARDDIR)/option_table.c \ + $(src)/arch/x86/stage1_mtrr.c \ + $(src)/arch/x86/amd/model_fxx/dualcore_id.c \ + $(src)/arch/x86/amd/model_fxx/stage1.c \ + $(src)/northbridge/amd/k8/coherent_ht.c \ + $(src)/northbridge/amd/k8/libstage1.c \ + +INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ + $(src)/northbridge/amd/k8/raminit.c \ + $(src)/northbridge/amd/k8/dqs.c \ + $(src)/northbridge/amd/k8/reset_test.c \ + $(src)/northbridge/amd/k8/incoherent_ht.c \ + $(src)/arch/x86/pci_ops_conf1.c \ + $(src)/arch/x86/stage1_mtrr.c \ + $(src)/arch/x86/amd/model_fxx/dualcore.c \ + $(src)/arch/x86/amd/model_fxx/fidvid.c \ + $(src)/arch/x86/amd/model_fxx/init_cpus.c \ + $(src)/lib/clog2.c + + +STAGE2_MAINBOARD_SRC = + +$(obj)/coreboot.vpd: + $(Q)printf " BUILD DUMMY VPD\n" + $(Q)dd if=/dev/zero of=$(obj)/coreboot.vpd bs=256 count=1 $(SILENT) + Index: mainboard/amd/dbm690t/cmos.layout =================================================================== --- mainboard/amd/dbm690t/cmos.layout (revision 0) +++ mainboard/amd/dbm690t/cmos.layout (revision 0) @@ -0,0 +1,119 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 AMD +## Written by Yinghai Lu for AMD. +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +entries + +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +385 1 e 4 last_boot +386 1 e 1 ECC_memory +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 dual_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 reserved_memory + + + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 200Mhz +8 1 166Mhz +8 2 133Mhz +8 3 100Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 1007 1008 + + Index: southbridge/amd/rs690/Makefile =================================================================== --- southbridge/amd/rs690/Makefile (revision 0) +++ southbridge/amd/rs690/Makefile (revision 0) @@ -0,0 +1,33 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_RS690),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/rs690/cmn.c \ + $(src)/southbridge/amd/rs690/gfx.c \ + $(src)/southbridge/amd/rs690/ht.c \ + $(src)/southbridge/amd/rs690/pcie.c \ + $(src)/southbridge/amd/rs690/rs690.c + +STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/rs690/stage1.c + + +endif Index: southbridge/amd/sb600/Makefile =================================================================== --- southbridge/amd/sb600/Makefile (revision 0) +++ southbridge/amd/sb600/Makefile (revision 0) @@ -0,0 +1,40 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2007 coresystems GmbH +## (Written by Stefan Reinauer for coresystems GmbH) +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; either version 2 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB600),y) + +STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/sb600/sb600.c + +STAGE2_CHIPSET_SRC += \ + $(src)/southbridge/amd/sb600/ac97.c \ + $(src)/southbridge/amd/sb600/hda.c \ + $(src)/southbridge/amd/sb600/ide.c \ + $(src)/southbridge/amd/sb600/lpc.c \ + $(src)/southbridge/amd/sb600/pci.c \ + $(src)/southbridge/amd/sb600/sata.c \ + $(src)/southbridge/amd/sb600/sm.c \ + $(src)/southbridge/amd/sb600/usb.c + +STAGE0_CHIPSET_SRC += $(src)/southbridge/amd/sb600/stage1.c \ + $(src)/southbridge/amd/sb600/stage1_reset.c \ + $(src)/southbridge/amd/sb600/stage1_smbus.c + +endif Index: mainboard/amd/Kconfig =================================================================== --- mainboard/amd/Kconfig (revision 884) +++ mainboard/amd/Kconfig (working copy) @@ -35,6 +35,19 @@ help AMD DB800 Geode LX development board. +config BOARD_AMD_DBM690T + bool "dbm690t" + select ARCH_X86 + select OPTION_TABLE + select CPU_AMD_K8 + select NORTHBRIDGE_AMD_K8 + select SOUTHBRIDGE_AMD_SB600 + select SOUTHBRIDGE_AMD_RS690 + select SUPERIO_ITE/IT8712F + select IOAPIC + help + AMD dbm690t development board. + config BOARD_AMD_NORWICH bool "Norwich" select ARCH_X86