Author: rminnich
Date: 2008-10-05 06:46:32 +0200 (Sun, 05 Oct 2008)
New Revision: 888
Added:
coreboot-v3/superio/ite/it8712f/
coreboot-v3/superio/ite/it8712f/Makefile
coreboot-v3/superio/ite/it8712f/dts
coreboot-v3/superio/ite/it8712f/it8712f.h
coreboot-v3/superio/ite/it8712f/stage1.c
coreboot-v3/superio/ite/it8712f/superio.c
Modified:
coreboot-v3/superio/fintek/f71805f/dts
coreboot-v3/superio/fintek/f71805f/superio.c
coreboot-v3/superio/ite/it8716f/dts
coreboot-v3/superio/ite/it8716f/superio.c
coreboot-v3/superio/winbond/w83627hf/dts
coreboot-v3/superio/winbond/w83627hf/superio.c
Log:
All superios were broken in v3. Fix them by adding the right node to the
dts and making the ops struct non-static.
This is the second pass on this patch, I have put the changes in that
Uwe requested, I hope I got them all. I have not heard back from Uwe yet
but this patch is urgent.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Peter Stuge <[EMAIL PROTECTED]>
Modified: coreboot-v3/superio/fintek/f71805f/dts
===================================================================
--- coreboot-v3/superio/fintek/f71805f/dts 2008-10-03 20:10:29 UTC (rev
887)
+++ coreboot-v3/superio/fintek/f71805f/dts 2008-10-05 04:46:32 UTC (rev
888)
@@ -19,6 +19,7 @@
*/
{
+ device_operations = "f71805f_ops";
/* Floppy */
floppydev = "0x0";
floppyenable = "0";
Modified: coreboot-v3/superio/fintek/f71805f/superio.c
===================================================================
--- coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-03 20:10:29 UTC
(rev 887)
+++ coreboot-v3/superio/fintek/f71805f/superio.c 2008-10-05 04:46:32 UTC
(rev 888)
@@ -95,7 +95,15 @@
}
}
-static struct device_operations ops;
+struct device_operations f71805f_ops = {
+ .phase2_setup_scan_bus = phase2_setup_scan_bus,
+ .phase4_read_resources = pnp_read_resources,
+ .phase4_set_resources = f71805f_pnp_set_resources,
+ .phase4_enable_disable = f71805f_pnp_enable_resources,
+ .phase5_enable_resources = f71805f_pnp_enable,
+ .phase6_init = f71805f_init,
+};
+
static struct pnp_info pnp_dev_info[] = {
{ &ops, F71805F_SP1, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
{ &ops, F71805F_SP2, PNP_IO0 | PNP_IRQ0, { 0x7f8, 0 }, },
@@ -104,14 +112,5 @@
static void phase2_setup_scan_bus(struct device *dev)
{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+ pnp_enable_devices(dev, &f71805f_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
-
-static struct device_operations ops = {
- .phase2_setup_scan_bus = phase2_setup_scan_bus,
- .phase4_read_resources = pnp_read_resources,
- .phase4_set_resources = f71805f_pnp_set_resources,
- .phase4_enable_disable = f71805f_pnp_enable_resources,
- .phase5_enable_resources = f71805f_pnp_enable,
- .phase6_init = f71805f_init,
-};
Added: coreboot-v3/superio/ite/it8712f/Makefile
===================================================================
--- coreboot-v3/superio/ite/it8712f/Makefile (rev 0)
+++ coreboot-v3/superio/ite/it8712f/Makefile 2008-10-05 04:46:32 UTC (rev
888)
@@ -0,0 +1,29 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Peter Stuge <[EMAIL PROTECTED]>
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+ifeq ($(CONFIG_SUPERIO_ITE_IT8712F),y)
+
+STAGE0_CHIPSET_SRC += $(src)/superio/ite/it8712f/stage1.c
+STAGE0_CHIPSET_SRC += $(src)/device/pnp_raw.c
+
+# Always add to variables, as there could be more than one Super I/O.
+STAGE2_CHIPSET_SRC += $(src)/superio/ite/it8712f/superio.c
+
+endif
Added: coreboot-v3/superio/ite/it8712f/dts
===================================================================
--- coreboot-v3/superio/ite/it8712f/dts (rev 0)
+++ coreboot-v3/superio/ite/it8712f/dts 2008-10-05 04:46:32 UTC (rev 888)
@@ -0,0 +1,42 @@
+/*
+ *
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Ronald G. Minnich <[EMAIL PROTECTED]>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+{
+ device_operations = "it8712f_ops";
+ /* COM1 */
+ com1dev = "1";
+ com1enable = "0";
+ com1io = "0x3f8";
+ com1irq = "4";
+
+ /* COM2 */
+ com2dev = "2";
+ com2enable = "0";
+ com2io = "0x2f8";
+ com2irq = "3";
+
+ /* Keyboard */
+ kbdev = "5";
+ kbenable = "0";
+ kbio = "0x60";
+ kbio2 = "0x64";
+ kbirq = "1";
+ kbirq2 = "2";
+};
Added: coreboot-v3/superio/ite/it8712f/it8712f.h
===================================================================
--- coreboot-v3/superio/ite/it8712f/it8712f.h (rev 0)
+++ coreboot-v3/superio/ite/it8712f/it8712f.h 2008-10-05 04:46:32 UTC (rev
888)
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8712_2.asp */
+/* Status: Com1 is tested and works. */
+
+#define IT8712F_FDC 0x00 /* Floppy */
+#define IT8712F_SP1 0x01 /* Com1 */
+#define IT8712F_SP2 0x02 /* Com2 */
+#define IT8712F_PP 0x03 /* Parallel port */
+#define IT8712F_EC 0x04 /* Environment controller */
+#define IT8712F_KBCK 0x05 /* Keyboard */
+#define IT8712F_KBCM 0x06 /* Mouse */
+#define IT8712F_GPIO 0x07 /* GPIO */
+#define IT8712F_MIDI 0x08 /* MIDI port */
+#define IT8712F_GAME 0x09 /* GAME port */
+#define IT8712F_IR 0x0a /* Consumer IR */
+
Added: coreboot-v3/superio/ite/it8712f/stage1.c
===================================================================
--- coreboot-v3/superio/ite/it8712f/stage1.c (rev 0)
+++ coreboot-v3/superio/ite/it8712f/stage1.c 2008-10-05 04:46:32 UTC (rev
888)
@@ -0,0 +1,115 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <[EMAIL PROTECTED]>
+ * Copyright (C) 2008 Ronald G. Minnich <[EMAIL PROTECTED]>
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <io.h>
+#include <device/pnp.h>
+#include "it8712f.h"
+
+/* The base address is 0x2e or 0x4e, depending on config bytes. */
+#define SIO_BASE 0x2e
+#define SIO_INDEX SIO_BASE
+#define SIO_DATA SIO_BASE+1
+
+/* Global configuration registers. */
+#define IT8712F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */
+#define IT8712F_CONFIG_REG_LDN 0x07 /* Logical Device Number. */
+#define IT8712F_CONFIG_REG_CONFIGSEL 0x22 /* Configuration Select. */
+#define IT8712F_CONFIG_REG_CLOCKSEL 0x23 /* Clock Selection. */
+#define IT8712F_CONFIG_REG_SWSUSP 0x24 /* Software Suspend, Flash I/F. */
+#define IT8712F_CONFIG_REG_WATCHDOG 0x72 /* Watchdog control. */
+
+#define IT8712F_CONFIGURATION_PORT 0x2e /* Write-only. */
+
+/* The content of IT8712F_CONFIG_REG_LDN (index 0x07) must be set to the
+ LDN the register belongs to, before you can access the register. */
+void it8712f_sio_write(u8 ldn, u8 index, u8 value)
+{
+ outb(IT8712F_CONFIG_REG_LDN, SIO_BASE);
+ outb(ldn, SIO_DATA);
+ outb(index, SIO_BASE);
+ outb(value, SIO_DATA);
+}
+
+
+void it8712f_enter_conf(void)
+{
+ /* Enter the configuration state (MB PnP mode). */
+
+ /* Perform MB PnP setup to put the SIO chip at 0x2e. */
+ /* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+ /* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+ outb(0x87, IT8712F_CONFIGURATION_PORT);
+ outb(0x01, IT8712F_CONFIGURATION_PORT);
+ outb(0x55, IT8712F_CONFIGURATION_PORT);
+ outb(0x55, IT8712F_CONFIGURATION_PORT);
+}
+
+void it8712f_exit_conf(void)
+{
+ /* Exit the configuration state (MB PnP mode). */
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CC, 0x02);
+}
+
+
+void it8712f_24mhz_clkin(void)
+{
+ it8712f_enter_conf();
+
+ /* Select 24MHz CLKIN (48MHZ default)*/
+ it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CLOCKSEL, 0x1);
+
+ it8712f_exit_conf();
+
+}
+
+void it8712f_kill_watchdog(void)
+{
+ it8712f_enter_conf();
+
+ /* Kill the Watchdog */
+ it8712f_sio_write(0x07, IT8712F_CONFIG_REG_WATCHDOG, 0x00);
+
+ it8712f_exit_conf();
+}
+
+/* Enable the peripheral devices on the IT8712F Super I/O chip. */
+void it8712f_enable_serial(u32 dev, u16 iobase)
+{
+
+ /* (1) Enter the configuration state (MB PnP mode). */
+ it8712f_enter_conf();
+
+ /* (2) Modify the data of configuration registers. */
+
+ /* Select the chip to configure (if there's more than one).
+ Set bit 7 to select JP3=1, clear bit 7 to select JP3=0.
+ If this register is not written, both chips are configured. */
+ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_CONFIGSEL, 0x00); */
+
+ /* Enable serial port(s). */
+ it8712f_sio_write(IT8712F_SP1, 0x30, 0x1); /* Serial port 1 */
+ it8712f_sio_write(IT8712F_SP2, 0x30, 0x1); /* Serial port 2 */
+
+ /* Clear software suspend mode (clear bit 0). TODO: Needed? */
+ /* it8712f_sio_write(0x00, IT8712F_CONFIG_REG_SWSUSP, 0x00); */
+
+ /* (3) Exit the configuration state (MB PnP mode). */
+ it8712f_exit_conf();
+}
Added: coreboot-v3/superio/ite/it8712f/superio.c
===================================================================
--- coreboot-v3/superio/ite/it8712f/superio.c (rev 0)
+++ coreboot-v3/superio/ite/it8712f/superio.c 2008-10-05 04:46:32 UTC (rev
888)
@@ -0,0 +1,142 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Uwe Hermann <[EMAIL PROTECTED]>
+ * Copyright (C) 2007 Philipp Degler <[EMAIL PROTECTED]>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <io.h>
+#include <lib.h>
+#include <device/device.h>
+#include <device/pnp.h>
+#include <console.h>
+#include <string.h>
+#include <uart8250.h>
+#include <keyboard.h>
+#include <statictree.h>
+#include "it8712f.h"
+
+/* Base address 0x2e: 0x87 0x01 0x55 0x55. */
+/* Base address 0x4e: 0x87 0x01 0x55 0xaa. */
+static void pnp_enter_ext_func_mode(struct device * dev)
+{
+ outb(0x87, dev->path.pnp.port);
+ outb(0x01, dev->path.pnp.port);
+ outb(0x55, dev->path.pnp.port);
+
+ if (dev->dev->path.pnp.port == 0x4e) {
+ outb(0xaa, dev->path.pnp.port);
+ } else {
+ outb(0x55, dev->path.pnp.port);
+ }
+}
+
+static void pnp_exit_ext_func_mode(struct device * dev)
+{
+ pnp_write_config(dev, 0x02, 0x02);
+}
+
+static void it8712f_init(struct device * dev)
+{
+ struct superio_ite_it8712f_dts_config *conf;
+ struct resource *res0, *res1;
+
+ if (!dev->enabled) {
+ return;
+ }
+
+ conf = dev->chip_info;
+
+ switch (dev->path.u.pnp.device) {
+ case IT8712F_FDC: /* TODO. */
+ break;
+ case IT8712F_SP1:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com1);
+ break;
+ case IT8712F_SP2:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ init_uart8250(res0->base, &conf->com2);
+ break;
+ case IT8712F_PP: /* TODO. */
+ break;
+ case IT8712F_EC: /* TODO. */
+ break;
+ case IT8712F_KBCK:
+ res0 = find_resource(dev, PNP_IDX_IO0);
+ res1 = find_resource(dev, PNP_IDX_IO1);
+ set_kbc_ps2_mode();
+ init_pc_keyboard(res0->base, res1->base, &conf->keyboard);
+ break;
+ case IT8712F_KBCM: /* TODO. */
+ break;
+ case IT8712F_MIDI: /* TODO. */
+ break;
+ case IT8712F_GAME: /* TODO. */
+ break;
+ case IT8712F_IR: /* TODO. */
+ break;
+ }
+}
+
+static void it8712f_pnp_set_resources(struct device * dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void it8712f_pnp_enable_resources(struct device * dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_enable_resources(dev);
+ pnp_exit_ext_func_mode(dev);
+}
+
+static void it8712f_pnp_enable(struct device * dev)
+{
+ pnp_enter_ext_func_mode(dev);
+ pnp_set_logical_device(dev);
+ pnp_set_enable(dev, dev->enabled);
+ pnp_exit_ext_func_mode(dev);
+}
+
+struct device_operations it8712f_ops = {
+ .phase2_setup_scan_bus = it8712f_setup_scan_bus,
+ .phase4_read_resources = pnp_read_resources,
+ .phase4_set_resources = it8712f_pnp_set_resources,
+ .phase4_enable_disable = it8712f_pnp_enable_resources,
+ .phase5_enable_resources = it8712f_pnp_enable,
+ .phase6_init = it8712f_init,
+};
+
+/* TODO: FDC, MIDI, GAME, IR. */
+static struct pnp_info pnp_dev_info[] = {
+ {&ops, IT8712F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0}, },
+ {&ops, IT8712F_SP2, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0 | PNP_DRQ1, {0x7f8,
0}, },
+ {&ops, IT8712F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+ {&ops, IT8712F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8,
0x4},},
+ {&ops, IT8712F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0}, {0x7f8,
0x4}, },
+ {&ops, IT8712F_KBCM, PNP_IRQ0, },
+ {&ops, IT8712F_GPIO, },
+};
+
+static void it8712f_setup_scan_bus(struct device *dev)
+{
+ pnp_enable_devices(dev, &it8712f_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
+}
+
Modified: coreboot-v3/superio/ite/it8716f/dts
===================================================================
--- coreboot-v3/superio/ite/it8716f/dts 2008-10-03 20:10:29 UTC (rev 887)
+++ coreboot-v3/superio/ite/it8716f/dts 2008-10-05 04:46:32 UTC (rev 888)
@@ -20,6 +20,7 @@
*
*/
{
+ device_operations = "it8716f_ops";
/* Floppy */
floppydev = "0x0";
floppyenable = "0";
Modified: coreboot-v3/superio/ite/it8716f/superio.c
===================================================================
--- coreboot-v3/superio/ite/it8716f/superio.c 2008-10-03 20:10:29 UTC (rev
887)
+++ coreboot-v3/superio/ite/it8716f/superio.c 2008-10-05 04:46:32 UTC (rev
888)
@@ -108,28 +108,7 @@
pnp_exit_ext_func_mode(dev);
}
-static struct device_operations ops;
-static struct pnp_info pnp_dev_info[] = {
- {&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
- {&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
- {&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
- {&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
- {&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
- {0x7f8, 0x4},},
- {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
- {0x7ff, 0x4},},
- {&ops, IT8716F_KBCM, PNP_IRQ0,},
- {&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8,
0},},
- {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
- {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
- {&ops, IT8716F_IR,},
-};
-static void it8716f_setup_scan_bus(struct device *dev)
-{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
-}
-
static void it8716f_init(struct device *dev)
{
struct superio_ite_it8716f_dts_config *conf;
@@ -164,7 +143,7 @@
}
}
-static struct device_operations ops = {
+struct device_operations it8716f_ops = {
.phase2_setup_scan_bus = it8716f_setup_scan_bus,
.phase4_read_resources = pnp_read_resources,
.phase4_set_resources = it8716f_pnp_set_resources,
@@ -172,3 +151,24 @@
.phase5_enable_resources = it8716f_pnp_enable_resources,
.phase6_init = it8716f_init,
};
+
+static struct pnp_info pnp_dev_info[] = {
+ {&ops, IT8716F_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+ {&ops, IT8716F_SP1, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
+ {&ops, IT8716F_SP2, PNP_IO0 | PNP_IRQ0, {0x7f8, 0},},
+ {&ops, IT8716F_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0},},
+ {&ops, IT8716F_EC, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7f8, 0},
+ {0x7f8, 0x4},},
+ {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
+ {0x7ff, 0x4},},
+ {&ops, IT8716F_KBCM, PNP_IRQ0,},
+ {&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8,
0},},
+ {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
+ {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
+ {&ops, IT8716F_IR,},
+};
+
+static void it8716f_setup_scan_bus(struct device *dev)
+{
+ pnp_enable_devices(dev, &it8716f_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
+}
Modified: coreboot-v3/superio/winbond/w83627hf/dts
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/dts 2008-10-03 20:10:29 UTC (rev
887)
+++ coreboot-v3/superio/winbond/w83627hf/dts 2008-10-05 04:46:32 UTC (rev
888)
@@ -19,6 +19,7 @@
*/
{
+ device_operations = "w83627hf_ops";
/* To override any of these, put the over-ride in mainboard dts. */
/* Floppy */
Modified: coreboot-v3/superio/winbond/w83627hf/superio.c
===================================================================
--- coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-03 20:10:29 UTC
(rev 887)
+++ coreboot-v3/superio/winbond/w83627hf/superio.c 2008-10-05 04:46:32 UTC
(rev 888)
@@ -190,7 +190,15 @@
}
}
-static struct device_operations ops;
+struct device_operations w83627hf_ops = {
+ .phase2_setup_scan_bus = phase2_setup_scan_bus,
+ .phase4_read_resources = pnp_read_resources,
+ .phase4_set_resources = w83627hf_pnp_set_resources,
+ .phase4_enable_disable = w83627hf_pnp_enable_resources,
+ .phase5_enable_resources = w83627hf_pnp_enable,
+ .phase6_init = w83627hf_init,
+};
+
static struct pnp_info pnp_dev_info[] = {
{ &ops, W83627HF_FDC, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
{ &ops, W83627HF_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, { 0x07f8, 0}, },
@@ -209,14 +217,6 @@
static void phase2_setup_scan_bus(struct device *dev)
{
- pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info);
+ pnp_enable_devices(dev, &w83627hf_ops, ARRAY_SIZE(pnp_dev_info),
pnp_dev_info);
}
-static struct device_operations ops = {
- .phase2_setup_scan_bus = phase2_setup_scan_bus,
- .phase4_read_resources = pnp_read_resources,
- .phase4_set_resources = w83627hf_pnp_set_resources,
- .phase4_enable_disable = w83627hf_pnp_enable_resources,
- .phase5_enable_resources = w83627hf_pnp_enable,
- .phase6_init = w83627hf_init,
-};
--
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