On Sat, Oct 4, 2008 at 8:44 PM, Uwe Hermann <[EMAIL PROTECTED]> wrote:
> On Sun, Oct 05, 2008 at 01:27:01AM +0200, Vincent Legoll wrote: > > I'm trying to understand i855pm code, and reading reset_test.c, I see: > > #define MCH_DRC 0x70 > > > > whereas the 252613.pdf I downloaded from intel web site, at: > > http://www.intel.com/Assets/PDF/datasheet/252613.pdf > > "Intel(R) 855PM Chipset Memory Controller Hub (MCH) DDR 200/266 MHz > Datasheet" > > revision 003, page 71, has the following: > > > > 3.7.20. DRC – DRAM Controller Mode Register – Device #0 > > Offset: 7C-7Fh > > Default: 1000_0001h > > Access: Read/Write > > Size: 32 bits > > > > So what am I missing in the 0x70h versus 0x7Ch difference ? > > > > Could someone please gently enlighten me ? > > Looks like a typo to me, I guess in the code, but it could also be in > the datasheet. > > Be careful with the 855pm code though, I think it's unfinished and > possibly never ever worked. My understanding is that it's mostly a straight copy of and old version of i440bx that was somewhat fixed up but never completed. I'd avoid it like the plague. I'm pretty sure I requested removing it at one point, but it must have been shot down. -Corey > If you really plan to add support for some > newer Intel chipsets (which is not a small project mind you), I'd start > with the i3100 code, which is in good shape quality-wise and has been > confirmed working on hardware. > > > Uwe. > -- > http://www.hermann-uwe.de | http://www.holsham-traders.de > http://www.crazy-hacks.org | http://www.unmaintained-free-software.org > > -- > coreboot mailing list: [email protected] > http://www.coreboot.org/mailman/listinfo/coreboot >
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