Author: rminnich
Date: 2008-10-06 19:17:40 +0200 (Mon, 06 Oct 2008)
New Revision: 898
Modified:
coreboot-v3/mainboard/amd/Kconfig
coreboot-v3/mainboard/amd/serengeti/Makefile
coreboot-v3/mainboard/amd/serengeti/initram.c
Log:
delete commented out incorrect code in initram. Add dbm690t support to
amd/Kconfig. Fix serengeti Makefile.
dbe62 was tested and works i.e. this does no harm.
Signed-off-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Acked-by: Ronald G. Minnich <[EMAIL PROTECTED]>
Modified: coreboot-v3/mainboard/amd/Kconfig
===================================================================
--- coreboot-v3/mainboard/amd/Kconfig 2008-10-06 17:16:05 UTC (rev 897)
+++ coreboot-v3/mainboard/amd/Kconfig 2008-10-06 17:17:40 UTC (rev 898)
@@ -35,6 +35,19 @@
help
AMD DB800 Geode LX development board.
+config BOARD_AMD_DBM690T
+ bool "dbm690t"
+ select ARCH_X86
+ select OPTION_TABLE
+ select CPU_AMD_K8
+ select NORTHBRIDGE_AMD_K8
+ select SOUTHBRIDGE_AMD_SB600
+ select SOUTHBRIDGE_AMD_RS690
+ select SUPERIO_ITE_IT8712F
+ select IOAPIC
+ help
+ AMD dbm690t development board.
+
config BOARD_AMD_NORWICH
bool "Norwich"
select ARCH_X86
@@ -67,6 +80,11 @@
config MAINBOARD_DIR
string
+ default amd/dbm690t
+ depends BOARD_AMD_DBM690T
+
+config MAINBOARD_DIR
+ string
default amd/norwich
depends BOARD_AMD_NORWICH
@@ -74,4 +92,3 @@
string
default amd/serengeti
depends BOARD_AMD_SERENGETI
-
Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-06 17:16:05 UTC
(rev 897)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile 2008-10-06 17:17:40 UTC
(rev 898)
@@ -24,18 +24,19 @@
$(src)/mainboard/$(MAINBOARDDIR)/stage1.c \
$(src)/mainboard/$(MAINBOARDDIR)/option_table.c \
$(src)/arch/x86/stage1_mtrr.c \
+ $(src)/arch/x86/amd/model_fxx/dualcore_id.c \
+ $(src)/arch/x86/amd/model_fxx/stage1.c \
+ $(src)/northbridge/amd/k8/get_nodes.c \
+ $(src)/northbridge/amd/k8/libstage1.c \
$(src)/southbridge/amd/amd8111/stage1_smbus.c \
$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
- $(src)/arch/x86/amd/model_fxx/dualcore_id.c \
- $(src)/arch/x86/amd/model_fxx/stage1.c \
- $(src)/northbridge/amd/k8/coherent_ht.c \
- $(src)/northbridge/amd/k8/libstage1.c \
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \
$(src)/northbridge/amd/k8/dqs.c \
$(src)/northbridge/amd/k8/reset_test.c \
+ $(src)/northbridge/amd/k8/coherent_ht.c \
$(src)/northbridge/amd/k8/incoherent_ht.c \
$(src)/arch/x86/pci_ops_conf1.c \
$(src)/arch/x86/stage1_mtrr.c \
Modified: coreboot-v3/mainboard/amd/serengeti/initram.c
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/initram.c 2008-10-06 17:16:05 UTC
(rev 897)
+++ coreboot-v3/mainboard/amd/serengeti/initram.c 2008-10-06 17:17:40 UTC
(rev 898)
@@ -249,9 +249,6 @@
dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98);
#endif
-#warning re-implement post_cache_as_ram
- // post_cache_as_ram(); // bsp switch stack to ram and copy
sysinfo ram now
-
printk(BIOS_DEBUG, "stage1 returns\n");
return 0;
}
--
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