Author: hailfinger
Date: 2008-10-08 01:53:02 +0200 (Wed, 08 Oct 2008)
New Revision: 907
Modified:
coreboot-v3/arch/x86/amd/stage0.S
coreboot-v3/arch/x86/geodelx/stage0.S
coreboot-v3/arch/x86/i586/stage0.S
Log:
stage0 code for K8 and i586 has lots of mostly identical parts even in
CAR code.
Reduce the diff of the mostly identical parts to zero. That involves
changing comments, whitespace and instruction order.
Now we can split out the common parts more easily and concentrate on the
differences.
Signed-off-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Acked-by: Carl-Daniel Hailfinger <[EMAIL PROTECTED]>
Modified: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S 2008-10-07 23:13:49 UTC (rev 906)
+++ coreboot-v3/arch/x86/amd/stage0.S 2008-10-07 23:53:02 UTC (rev 907)
@@ -17,8 +17,14 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+
+/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
+
#define ASSEMBLY
#include <macros.h>
+#include <mtrr.h>
+#include <amd/k8/k8.h>
+
#define CacheSize CONFIG_CARSIZE
#define CacheBase CONFIG_CARBASE
#define MEM_TOPK 2048
@@ -32,9 +38,6 @@
#define CacheSizeAPStack 0x400 /* 1K */
#endif
-#include <mtrr.h>
-#include <amd/k8/k8.h>
-
.code16
.globl _stage0
_stage0:
@@ -239,13 +242,13 @@
clear_fixed_var_mtrr:
lodsl (%esi), %eax
testl %eax, %eax
- jz clear_fixed_var_mtrr_out
+ jz clear_fixed_var_mtrr_out
movl %eax, %ecx
xorl %eax, %eax
wrmsr
- jmp clear_fixed_var_mtrr
+ jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment.
@@ -304,14 +307,14 @@
#endif
#if CacheSize > 0x8000
- /* enable caching for 32K-64K using fixed mtrr */
- movl $0x268, %ecx /* fix4k_c0000*/
+ /* enable caching for 32K-64K using fixed mtrr */
+ movl $0x268, %ecx /* fix4k_c0000*/
simplemask CacheSize, 0x8000
- wrmsr
+ wrmsr
#endif
- /* enable caching for 0-32K using fixed mtrr */
- movl $0x269, %ecx /* fix4k_c8000*/
+ /* enable caching for 0-32K using fixed mtrr */
+ movl $0x269, %ecx /* fix4k_c8000*/
simplemask CacheSize, 0
wrmsr
@@ -436,12 +439,15 @@
/* Restore the BIST result. */
movl %ebp, %eax
- /* We need to set ebp ? No need */
+ /* We need to set ebp? No need. */
movl %esp, %ebp
- pushl %ebx /* init detected */
- pushl %eax /* bist */
+
+ /* Second parameter: init_detected */
+ pushl %ebx
+ /* First parameter: bist */
+ pushl %eax
call stage1_main
- /* We will not go back */
+ /* We will not go back. */
movb $0xAF, %al /* Should never see this postcode */
outb %al, $0x80
@@ -462,7 +468,6 @@
.long 0xC001001A, 0xC001001D
.long 0x000 /* NULL, end of table */
-cache_as_ram_setup_out:
/* Reset vector. */
/*
Modified: coreboot-v3/arch/x86/geodelx/stage0.S
===================================================================
--- coreboot-v3/arch/x86/geodelx/stage0.S 2008-10-07 23:13:49 UTC (rev
906)
+++ coreboot-v3/arch/x86/geodelx/stage0.S 2008-10-07 23:53:02 UTC (rev
907)
@@ -92,7 +92,7 @@
.byte 0x00, 0x93, 0xcf, 0x00
gdt16xend:
- /* From now on we are 32bit. */
+ /* From now on we are 32 bit. */
.code32
/* We have two gdts where we could have one. That is ok.
@@ -365,15 +365,17 @@
movl $0, %eax
pushl %eax
- /* Store zero for the unused init_detected parameter. */
- pushl %eax
-
/* Restore the BIST result. */
movl %ebp, %eax
/* We need to set ebp? No need. */
movl %esp, %ebp
- pushl %eax /* BIST */
+
+ /* Second parameter: init_detected */
+ /* Store zero for the unused init_detected parameter. */
+ pushl $0
+ /* First parameter: bist */
+ pushl %eax
jmp stage1_main
/* We will not go back. */
Modified: coreboot-v3/arch/x86/i586/stage0.S
===================================================================
--- coreboot-v3/arch/x86/i586/stage0.S 2008-10-07 23:13:49 UTC (rev 906)
+++ coreboot-v3/arch/x86/i586/stage0.S 2008-10-07 23:53:02 UTC (rev 907)
@@ -23,7 +23,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-# init code - switch cpu to pmode and enable cache as ram.
+/* Init code - Switch CPU to protected mode and enable Cache-as-Ram (CAR). */
#include <macros.h>
@@ -277,7 +277,7 @@
movl $0x00000c00, %eax
wrmsr
- /*Clear all MTRRs */
+ /* Clear all MTRRs */
xorl %edx, %edx
movl $fixed_mtrr_msr, %esi
clear_fixed_var_mtrr:
@@ -289,7 +289,7 @@
xorl %eax, %eax
wrmsr
- jmp clear_fixed_var_mtrr
+ jmp clear_fixed_var_mtrr
clear_fixed_var_mtrr_out:
/* 0x06 is the WB IO type for a given 4k segment.
@@ -305,13 +305,13 @@
*/
xorl \reg, \reg
.elseif \segs == 1
- movl $0x06000000, \reg
+ movl $0x06000000, \reg /* WB IO type */
.elseif \segs == 2
- movl $0x06060000, \reg
+ movl $0x06060000, \reg /* WB IO type */
.elseif \segs == 3
- movl $0x06060600, \reg
+ movl $0x06060600, \reg /* WB IO type */
.elseif \segs >= 4
- movl $0x06060606, \reg
+ movl $0x06060606, \reg /* WB IO type */
.endif
.endm
@@ -439,16 +439,20 @@
movl $0, %eax
pushl %eax
- /* Store zero for the unused init_detected parameter. */
- pushl %eax
-
/* Restore the BIST result. */
movl %ebp, %eax
- /* We need to set ebp ? No need */
+
+ /* We need to set ebp? No need. */
movl %esp, %ebp
- pushl %eax /* bist */
- call stage1_main
- /* We will not go back */
+
+ /* Second parameter: init_detected */
+ /* Store zero for the unused init_detected parameter. */
+ pushl $0
+ /* First parameter: bist */
+ pushl %eax
+ call stage1_main
+ /* We will not go back. */
+
fixed_mtrr_msr:
.long 0x250, 0x258, 0x259
.long 0x268, 0x269, 0x26A
--
coreboot mailing list: [email protected]
http://www.coreboot.org/mailman/listinfo/coreboot
